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Electrical Electonics and Comunication Engineering EEE ECE

VLSI Design - EC6601

VLSI Design

MOS TRANSISTOR PRINCIPLE

COMBINATIONAL LOGIC CIRCUITS


-:- Circuit Families and Its Comparison
-:- Low Power Logic Design
-:- Sequencing Static Circuits
-:- Circuit Design of Latches and Flip Flops
-:- Static Sequencing Element Methodology
-:- Sequencing Dynamic Circuits
-:- Synchronizers - VLSI Design
-:- Important Short Questions and Answers: Combinational and Sequential Circuit Design

SEQUENTIAL LOGIC CIRCUITS


-:- Circuit Families and Its Comparison
-:- Low Power Logic Design
-:- Sequencing Static Circuits
-:- Circuit Design of Latches and Flip Flops
-:- Static Sequencing Element Methodology
-:- Sequencing Dynamic Circuits
-:- Synchronizers - VLSI Design
-:- Important Short Questions and Answers: Combinational and Sequential Circuit Design

DESIGNING ARITHMETIC BUILDING BLOCKS

IMPLEMENTATION STRATEGIES

CMOS TECHNOLOGY


-:- A Brief History of CMOS Technology
-:- MOS Transistor
-:- Ideal I-V characteristics of MOS Transistor
-:- CV characteristics
-:- Non ideal I-V effects
-:- DC Transfer Characteristics of CMOS Inverter
-:- CMOS Technologies
-:- BiCMOS Technology Fabrication
-:- CMOS Layout Design Rules
-:- CMOS Process Enhancements
-:- Technology Related CAD Issues - CMOS Technology
-:- Manufacturing Issues - CMOS Technology
-:- Important Short Questions and Answers: VLSI Design - CMOS Technology

CIRCUIT CHARACTERIZATION AND SIMULATION


-:- Delay Estimation
-:- Logical Effort
-:- Transistor Sizing
-:- Power Dissipation - VLSI Design
-:- Interconnect - VLSI Design
-:- Design Margin - VLSI Design
-:- Reliability - VLSI Design
-:- Scaling - VLSI Design
-:- Spice Tutorial
-:- Device Models - VLSI Design
-:- Device and Circuit Characterization
-:- Interconnect Simulation
-:- Important Short Questions and Answers: Circuit Characterization and Simulation

COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN


-:- Circuit Families and Its Comparison
-:- Low Power Logic Design
-:- Sequencing Static Circuits
-:- Circuit Design of Latches and Flip Flops
-:- Static Sequencing Element Methodology
-:- Sequencing Dynamic Circuits
-:- Synchronizers - VLSI Design
-:- Important Short Questions and Answers: Combinational and Sequential Circuit Design

CMOS TESTING


-:- Need For Testing
-:- Testers and Test Programs
-:- Text Fixtures
-:- Logic Verification
-:- Silicon Debug Principal
-:- Manufacturing Test
-:- Designs For Testability
-:- Boundary Scan
-:- Important Short Questions and Answers: VLSI Design - CMOS Testing

SPECIFICATION USING VERILOG HDL


-:- Specification Using Verilog HDL: Basic Concepts
-:- Identifiers - verilog code
-:- Gate Primitives
-:- Gate Delays - Verilog HDL
-:- Operators - Verilog HDL
-:- Timing Controls - Verilog HDL
-:- Procedural Assignments Conditional Statements
-:- Data Flow and RTL
-:- Structural Gate Level Switch Level Modeling
-:- Design Hierarchies - VLSI Design
-:- Behavioural and RTI Modeling
-:- Testbenches
-:- Structural Gate Level Description of Decoder
-:- Important Short Questions and Answers: Specification Using Verilog HDL
-:- Important Short Questions and Answers: VLSI Design