Low Power Logic Design

LOW POWER LOGIC DESIGN:

Is to reduce dynamic power and static power in a circuit

§   a:

§   C:

§   VDD:

§   f:

Reduce static power, Reduce dynamic power

§   a: clock gating, sleep mode

§   C: small transistors (esp. on clock), short wires

§   VDD:

§   f:

Reduce static power, Reduce dynamic power

§   a: clock gating, sleep mode

§   C: small transistors (esp. on clock), short wires

§   VDD: lowest suitable voltage

§   f: lowest suitable frequency

Reduce static power

§   Selectively use ratioed circuits

§   Selectively use low Vt devices

§   Leakage reduction: stacked devices, body bias, low temperature.