IMPORTANT QUESTIONS & ANSWERS
1. What are four generations of Integration Circuits?
_ SSI (Small Scale Integration)
_ MSI (Medium Scale Integration)
_ LSI (Large Scale Integration)
_ VLSI (Very Large Scale Integration)
2. Give the advantages of IC?
_ Size is less
_ High Speed
_ Less Power Dissipation
3. Give the variety of Integrated Circuits?
_ More Specialized Circuits
_ Application specific Integrated Circuits(ASICs)
4. Give the basic process for IC fabrication
_ Silicon wafer Preparation
_ Epitaxial Growth
_ Ion Implantation
_ Isolation technique
_ Assembly processing & Packaging
5. What are the various Silicon wafer Preparation?
_ Crystal growth & doping
_ Ingot trimming & grinding
_ Ingot slicing
_ Wafer polishing & etching
_ Wafer cleaning.
6. Different types of oxidation?
Dry & Wet Oxidation
7. What is the transistors CMOS technology provides?
n-type transistors & p-type transistors.
8. What are the different layers in MOS transistors?
Drain , Source & Gate
9. What is Enhancement mode transistor?
The device that is normally cut-off with zero gate bias.
10. What is Depletion mode Device?
Device that conduct with zero gate bias.
11. When the channel is said to be pinched –off?
If a large Vds is applied this voltage with deplete the Inversion layer .This Voltage effectively pinches off the channel near the drain.
12. Give the different types of CMOS process?
_ p-well process
_ n-well process
_ Silicon-On-Insulator Process
_ Twin- tub Process
13.What are the steps involved in twin-tub process?
_ Tub Formation
_ Thin-oxide Construction
_ Source & Drain Implantation
_ Contact cut definition
14.What are the advantages of Silicon-on-Insulator process?
_ No Latch-up
_ Due to absence of bulks transistor structures are denser than bulk silicon.
15.What is BiCMOS Technology?
It is the combination of Bipolar technology & CMOS technology.
16.What are the basic processing steps involved in BiCMOS process?
Additional masks defining P base region
_ N Collector area
_ Buried Sub collector (SCCD)
_ Processing steps in CMOS process
17.What are the advantages of CMOS process?
Low power Dissipation
High Packing density
Bi directional capability
18.What are the advantages of CMOS process?
Low Input Impedance
Low delay Sensitivity to load.
19.What is the fundamental goal in Device modeling?
To obtain the functional relationship among the terminal electrical variables of the device that is to be modeled.
20.Define Short Channel devices?
Transistors with Channel length less than 3- 5 microns are termed as Short channel devices. With short channel devices the ratio between the lateral & vertical dimensions are reduced.
21.What is pull down de vice?
A device connected so as to pull the output voltage to the lower supply voltage usually 0V is called pull down de vice.
22.What is pull up devic e?
A device connected so as to pull the output voltage to the upper supply voltage usually VDD is called pull up device.
23. Why NMOS technolo gy is preferred more than PMOS technolo gy?
N- channel transistors has greater switching speed when compared tp PMOS transistors.
24. What are the different operating regions foe an MOS transistor?
_ Cutoff region
_ Non- Saturated Region
_ Saturated Region
25. What are the differ ent MOS layers?
26.What is Stick Diagra m?
It is used to convey information through the use of color code. Als o it is the cartoon of a chip layout.
27.What are the uses of Stick diagram?
_ It can be drawn much easier and faster than a complex layout .
_ These are especi ally important tools for layout built from large cells.
28.Give the various col or coding used in stick diagram?
_ Green – n-diffusion
_ Red- polysilicon
_ Blue –metal
_ Yellow- implant
_ Black-contact areas.
30.Define Threshold volta ge in CMOS?
The Threshold voltage, V for a MOS transistor can be defined as the voltage applied between the gate and the source of the MOS transistor below which the drain to source current, IDSeffectively drops to zero.
31.What is Body effect?
The threshold volatge V T is not a constant w. r. to the vol tage difference
between the substrate and the source of MOS transistor. This e ffect is called substrate-bias effect or body effect.
32.What is Channel-leng th modulation?
The current between drain and source terminals is constant and independent of the applied voltage over the terminals. This is not entirely correct. The effective length of the conductive channel is actu ally modulated by the applied VDS i,ncreasing VDS causes the
depletion region at the drain junction to grow, reducing the length of th e effective channel.
33. What is Latch – up?
Latch up is a condition in which the parasitic components give rise to the establishment of low resiistance conducting paths between V and V with disastrous
Latch up is a condition in which the parasitic components give rise to the establishment of low resiistance conducting paths between VDD
with disastrousresults. Careful control during fabrication is necessary to avoid this problem.
36.Define Rise time
Rise time, tr is the time ta ken for a waveform to rise from 10% to 90% of its steady-state value.
37. Define Fall time
Fall time, tf is the time taken for a waveform to fall from 90% to 10% of its steady-state value.
38. Define Delay time
Delay time, td is the time difference between input transition (50%) a nd the 50% output level. This is the time taken for a logic transition to pass from input to output.
39. What are two components of Power dissipation.
There are two com ponents that establish the amount of power dissipated in a CMOS circuit. These are:
i) Static dissipation due to leakage current or other current drawn continuously from the power supply.
ii) Dynamic dissipation due to - Switchi ng transient current – Charging and discharging of load capacitances.
40. Give some of the important CAD tools.
Some of the important CAD tools are:
i) Layout editors
ii) Design Rule checkers (DRC)
iii) Circuit extrraction
41.What is Verilog?
Verilog is a general purpose hardware descriptor language. It is similar in syntax to the C programming language. It can be used to model a digital system at many levels of abstractio n ranging from the algorithmic level to the s witch level.
42. What are the various modeling used in Verilog?
1. Gate-level modeling
2. Data-flow modeling
3. Switch-lev el modeling
4. Behavioral modeling
43. What is the structural gate-level modeling?
Structural modeling describes a digital logic networks in terms of the components that make up the system. Gate-level modeling is based on using primitive logic gates and specifying how they are wired together.
44.What is Switch-level modeling?
Verilog allows switch-level modeling that is based on the behavior of MOSFETs. Digital circuits at the MOS-transistor level are described using the MOSFET switches.
45. What are identifiers?
Identifiers are names of modules, variables and other objects that we can reference in the design. Identifiers consists of upper and lower case letters, digits 0 through 9, the underscore character(_) and the dollar sign($). It must be a single group of characters.