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Chapter: VLSI Design : Specification Using Verilog HDL

Important Short Questions and Answers: Specification Using Verilog HDL

VLSI Design - Specification Using Verilog HDL - Important Short Questions and Answers: Specification Using Verilog HDL


1)Write the acronym for VHDL?


VHDL is an acronym for VHSIC Hardware Description Language (VHSIC is an acronym for Very High Speed Integrated Circuits).


2) What are the different types of modeling VHDL?


1)       Structural modeling


2)       Data flow modeling


3)       behavioral modeling


4)       Mixed type of modeling


3) What is packages and what is the use of these packages


A package declaration is used to store a set of common declaration such as components types procedures and functions these declaration can then be imported into others design units using a use caluse.


4) What is variable class ,give example for variable


An object of variable class can also hold a single value of a given type , However in this case different values can be assigned to a variable at different time.


Ex:variable ss: integer;


5) Name two subprograms and give the difference between these two.


1)       Function 2) procedure


Only one output is possible in function..


Many outputs possible using procedure


6) What is subprogram Overloading


If two or more subprogram to be executed in a same name. overloading of subprogram should be performed.


7) What are the different kinds of The test bench


Stimulus only Full testbench Simulator specific Hybrid testbench Fast testbench


6. write the VHDL coding for a sequential statement (d-flipflop )

entity dff is


port(clk,d:in std_logic;


q:out std_logic);




architecture dff of dff is








if clk’ event and clk=’ 1’ then




end process;




9) What is Moore FSM


The output of a Moore finite state machine(FSM) depends only on the state and not on its inputs. This type of behaviour can be modeled using a single process with the case statement that switches on the state value.


10) Write the testbench for and gate


entity testand2 is


end entity


architecture io of testand2 is


signal a,b,c:std_logic;




g1:entity work.and2(ex2) port map(a,b,c) a<=’ 0’ ,’ 1’ after 100 ns;


b<=’ 0’ , ‘1’ after 150 ns;




11. write the syntax of procedure body?


Procedure procedure name (parameterlist)

12. What is test bench?


A test bench is a model which is used to exercise and verify the correctness of a hardware model.


13.   What are the two methods to generate stimulus values?


i.          To create waveforms and apply stimulus at discrete time intervals.

ii.        To generate stimulus based on the state of the entity or output of the entity.


14.   Differentiate between channeled & channel less gate array.


Channeled Gate Array Channel less Gate Array

1. Only the interconnect is customized only the top few mask layers are customized.


2. The interconnect uses predefined spaces between rows of base cells. No predefined areas are set aside for routing between cells.


3. Routing is done using the spaces Routing is done using the area of transistors unused.

4. Logic density is less Logic density is higher.


15. What is a FPGA?


A field programmable gate array (FPGA) is a programmable logic device that supports implementation of relatively large logic circuits. FPGAs can be used to implement a logic circuit with more than 20,000 gates whereas a CPLD can implement circuits of upto about 20,000 equivalent gates.


16. What are the different methods of programming of PALs?


The programming of PALs is done in three main ways:

Fusible links


UV – erasable EPROM

EEPROM (E2PROM) – Electrically Erasable Programmable ROM


17.What is an antifuse?


An antifuse is normally high resistance (>100MW). On application of appropriate programming voltages, the antifuse is changed permanently to a low-resistance structure (200-500W).


18. What are the different levels of design abstraction at physical design.

Architectural or functional level

Register Transfer-level (RTL)

Logic level

Circuit level


19.What are macros?

The logic cells in a gate-array library are often called macros.


20. What are Programmable Interconnects?


In a PAL, the device is programmed by changing the characteristics if the switching element. An alternative would be to program the routing.

21. Give the steps inASIC design flow.


a. Design entry

b. Logic synthesisSystem partitioning

c. Prelayout simulation.

d. Floorplanning

e. Placement

f. Routing

g. Extraction


22. Write notes on functionality tests?


Functionality tests verify that the chip performs its intended function. These tests assert that all the gates in the chip, acting in concert, achieve a desired function. These tests are usually used early in the design cycle to verify the functionality of the circuit.


23. Write notes on manufacturing tests?


Manufacturing tests verify that every gate and register in the chip functions correctly. These tests are used after the chip is manufactured to verify that the silicon is intact.


24. Mention the defects that occur in a chip?


a) layer-to-layer shorts

b) discontinuous wires

c) thin-oxide shorts to substrate or well


25. Give some circuit maladies to overcome the defects?


a. nodes shorted to power or ground

b. nodes shorted to each other

c.  inputs floating/outputs disconnected


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