Behavioural and RTI Modeling

BEHAVIOURAL AND RTL  MODELING

In this section we are going to discuss about the behavioural features of Verilog.

1. Modules

A circuit or subcircuit can be explained in verilog is called a module. The general structure of a module declaration is given below:

modulemodule_name [(port_name {, port_name})]; [parameter declarations]

[input declarations] [output declarations] [inout declarations]

[wire or tri declarations] [reg or integer declarations] [function or task declarations] [assign continuous assignments] [initial block]

[always blocks] [gate instantiations] [module instantiations] endmodule

General form of a module

The module has name, module_name, which can be any valid identifier followed by a list of ports. The name port refers to an input or output connection in an electrical circuit.

The ports used in verilog code are:

a)   input port

b)   output port

c)   inout port

these ports can be either scalar or vector.

Example:

inputa,b,c; input [2:0]a,b; output s,c; inout [5:0]q; output [3:0]s; wire x,y;

wire [5:0]y;

reg [ 2:0]x;

All procedural statements occur in blocks that are defined inside modules. There are two kinds of procedural blocks: the initial block and the always block.

Within each block, Verilog uses a begin and end to enclose the statements. Since initial blocks are ignored during synthesis, only always blocks are discussed.

Always blocks usually take the following format:

always begin statement

..... end

where each statement is a procedural assignment line terminated by a semicolon

2. Module Declaration

In the module declaration, the I/O ports of the circuit are declared. Each port has a name and a mode

(in, out, and inout) as shown in the example below.

module ex (A, B, C, D, E);

input A, B, C;

output D; inout E; wire D, E;

...

assign E = oe ? A : 1'bz;

assign D = B & E;

... endmodule

The input and output ports defined in the module declaration called ex are the basic input and output I/O signals for the design.

The inout port in Verilog is analogous to a bi-directional I/O pin on the device with the data flow for output versus input being controlled by the enable signal to the tristate buffer.

The preceding example describes E as a tristate buffer with a high-true output enable signal. If oe = 1, the value of signal A will be output on the pin represented by E. If oe = 0, then the buff er is in high impedance (Z) and any input value driven on the pin E (from the external logic) will be brought into the device and fed to the signal represented by D.

3. Verilog Assignments

There are two forms of assignment statements in the Verilog language:

•        Continuous Assignments

•        Procedural Assignments

4. Continuous Assignments

Continuous assignments are used to model combinatorial logic in a concise way. Both explicit and implicit continuous assignments are supported. Explicit continuous assignments are introduced by the assign keyword after the net has been separately declared. Implicit continuous assignments combine declaration and assignment.

Example of an explicit continuous assignment:

Example of an implicit continuous assignment:

wiretemp_hold = a | b;

Note Continuous assignments are only allowed on wire and tri data types.

5. Procedural Assignments

Procedural assignments are used to assign values to variables declared as regs and are introduced by always blocks, tasks, and functions. Procedural assignments are usually used to model registers and FSMs.

Different statements can be used in a process:

•        Variable and signal assignment

•        If... else statement

•        Case statement

•        For loop statement

•        Function and task call

The following sections provide examples of each of these statements.

6. if...else statement

If... else statements use true/false conditions to execute statements. If the expression evaluates to true, the first statement is executed. A block of multiple statements may be executed using begin and end keywords. If...else statements may be nested. The following example shows how a MUX can be described using an If...else statement.

Example MUX Description Using If... Else Statement

module mux4 (sel, p, q, r, s, y);

input [1:0] sel;

input [1:0] p, q, r, s;

output [1:0] y;

reg [1:0] y;

always @(sel or p or q or r or s)

begin

if (sel[1])

if (sel[0])

y = s;

else

y = r;

else

if (sel[0])

y = q;

else

y = p;

end endmodule

7. Case statement

Case statements perform a comparison to an expression to evaluate one of anumber of parallel branches. The Case statement evaluates the branches in the order they are written. The first branch that evaluates to true is executed. If none of the branches match, the default branch is executed.

Note Do no use unbounded integers in case statements. Always bound integers to a specific number of bits, or results will be unpredictable.

Caseztreats all z values in any bit position of the branch alternative as a don't care.

Casextreats all x and z values in any bit position of the branch alternative as a don't care.

The question mark (?) can be used as a "don't care" in any of the preceding case statements. The following example shows how a MUX can be described using a Case statement.