Procedural Assignments Conditional Statements

PROCEDURAL ASSIGNMENTS CONDITIONAL STATEMENTS

Verilog provides procedural statements. Procedural statements are executed in which order they appear in the code. Verilog syntax requires that procedural statements be contained inside an always block.

1. Always blocks:

An always block is a construct that contains one or more procedural statements. It has the form:

always @ (sensitivity_list) [begin]

[procedural assignment statements] [if-else statements]

[case statements]

[while, repeat, and for loops] [task and function calls]

[end]

Verilog includes several types of procedural statements. When multiple statements are included in an always block, the begin and end keywords are used, otherwise it can be omitted.

The sensitivity_list is a list of signals that directly affect the output r esults generated by the always block.

Example for always block:

always @ (a or b)

begin

end

sum = a ^ b;

carry = a & b;

Since the  output  variables  sum  and carry  depend  on a  and b,  these signals  are included in

the sensitivity list, separated by a keyword or.If the value of a signal in the sensitivity list changes, then the statements inside the always block are evaluated in the order presented.

2. Procedural assignment statements:

Any signal assigned a value inside an always block has to be a variable of type reg or integer. A value is assigned to a variable with a procedural assignment statement. There are two types of assignments:

a)        blocking assignments

b)       non-blocking assignments

Blocking assignments are denoted by the symbol (=).

The term blocking means that the assignment statement completes and updates its left – hand side before the subsequent statement is evaluated.

Example:

sum = a + b;

x = sum [0];

The first statement sets sum using the current values of a and b, and then the second statement sets p according to this new value of sum.

Verilog also provides non-blocking assignments and it can be denoted by (<=). Example:

s <= a + b;

p <= s [0];

At simulation time ti, the statements are still evaluated in order, but they both use the values of variables that exist at the start of the simulation time, ti.

The first statement determines a new value for s based on the current values of a and b, but s is not actually changed to this value until all statements in the associated always block have been evaluated. So, the value of p at time ti is based on the value of s at time ti-1.

For blocking assignments, the values of variables seen at time ti by each statement are the new values set in ti by any preceding statements in the always block ti-1.For non-blocking assignments, the values of variables seen at time ti are the values set in time

3. The if-else statement:

General form of the if-else statement is given in figure.

if (expression 1)

begin

end

statement;

else if (expression 2)

begin

end else

begin

statement;

end

statement;

If expression 1 is true, then the first statement is evaluated. When multiple statements are involved, they have to be included inside a begin-end block.