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1. Verilog HDL:
Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). A hardware description Language is a language used to describe a digital system, for example, a microprocessor or a memory or simple flip-flop. This just means that by using a HDL one can describe any hardware (digital) at any level.
2. White space:
White space characters, such as SPACE and TAB and blank lines are ignored by verilog compiler. Multiple statements are written on a single line such as,
f = a0; if (s == 0) f = a1;
Placing each statement on a separate line and using indentation within blocks of code, such as an if-else statement are good ways to increase the readability of code.
3. Documentation in verilog code:
Documentation can be included in verilog code by writing a comment.A short comment begins with double slash, //, and continues to the end of the line. A long comment can span multiple lines and is contained inside the delimiters /* and */.
//this is a short comment
/* this is a long comment
That spans two lines */
Verilog has operators of three types. They are unary operators which precede the operand, binary operators which appear between two operands and ternary operators that have two separate operators that separate three operands.
x = + y; //+ is unary operator, y is the operand
x = y && z; // && is a binary operator, y and z are operands x = a ?b : c; // ? : is a ternary operator, a, b, c are operands
5. Signal values, Numbers:
Verilog supports scalar nets and variables that can be represent individual signals and vectors that correspond to multiple signals. Each individual signal can have four possible values:
0 = logic value 0;
1 = logic value 1;
z = high impedance;
x = unknown value;
The value of a vector variable is specified by giving a constant of the form
where size is the number of bits in the constant and resix is the number base.
d = decimal;
b = binary;
h = hexadecimal;
o = octal;
when no radix is specified the default is decimal.
0 number 0;
10 decimal number 10;
’b10 binary number 10 = (2)10;
’h10 hex number 10 = (16)10;
4’b100 binary number 0100 = (4)10;
4’bx unknown 4 bit value xxxx;
8’hfx equivalent to 8’b1111_xxxx;
A parameter in verilog associates an identifier name with a constant. Declaration: parameter n = 4;
parameter s0 = 2’b00, s1 = 2’b 01; s2 =2’b11; s3 = 2’b 10;
A net represents a node in a circuit. There are two different types of nets are used in verilog. They are wire and tri.
Wire type net can be employed to connect an output of one logic element in a circuit to an input of another logic element. Examples of scalar wire declarations:
wire a, b; Example of vector wire declaration: wire [2:0] s;
wire [1:3] x;
The net s can be used as a three bit quantity or each bit can be referred to individually as s, s and s. If a value assigned to s such as s = 3’b010, the result is s = 0, s = 1 and s = 0.
The tri type denotes circuit nodes that are connected in a tri state fashion. Example:
tri [7:0] out;
These nets are treated in the same manner as the wire type and they are used only to enhance the readability of code includes tri state gates.
A variable can be assigned a value in one verilog statement and it retains this value until it is overwritten in a subsequent assignment statement. There are two types of variables, reg and integer.
reg [2:0] out;
The above declarations show that out has three bits. The keyword reg does not denote a storage element or register. In verilog code reg variables can be used to model either combinational or sequential parts of a circuit.
Integer variables are useful for describing the behaviour of a module, but they do not directly correspond to nodes in a circuit.
Memory is a two dimensional array of bits. Verilog allows such a structure to be declared as a variable (reg or integer) that is an array of vectors, such as
reg[3:0] x [1:0]
This statement defines x as two four-bit variables named x and x. Memories cannot be net types and they cannot be used as ports on a module.
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