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Chapter: VLSI Design : CMOS Testing

Identifiers - verilog code

Identifiers are the names of variables and other elements in verilog code.

IDENTIFIERS

 

Rules:

 

Identifiers are the names of variables and other elements in verilog code.

 

a)        Any letter or digit may be used

 

b)       The _underscore and $ characters are used

 

c)        Identifiers must not begin with a digit and it should not be a verilog keyword 


Example: legal identifiers are a, x1, a_b and byte.

 

 

Illegal identifiers are 1a, +b, a*b and 258.

 

Verilog is case sensitive, hence k is not the same as K and BYTE is not the same as Byte.

 

Verilog allows a second form of identifier called an escaped identifier. These identifiers are begin with (\) backslash character, which can then be followed by any printable ASCII characters except white spaces.

 

Example: \234, \sig-name, \x+y

 

Escaped identifiers should not be used in normal verilogcode, they are intended for use in code produced automatically when other languages are translated into verilog.

 

Structural level modeling:

 

In gate level modeling or structural level modeling, the circuit is described in terms of logic gates. Example: and, or, nand, nor, etc... The logic gates have one scalar output and multiple scalar inputs. The first terminal in the list of gate terminals is an output and the other terminals are inputs.


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