NEED FOR TESTING:
testing is a method for testing CMOS integrated circuits for the presence of
manufacturing faults. It relies on measuring the supply current (Idd) in the
quiescent state (when the circuit is not switching and inputs are held at
current consumed in the state is commonly called Iddq for Idd (quiescent) and
hence the name.
testing uses the principle that in a correctly operating quiescent CMOS digital
circuit, there is no static current path between the power supply and ground,
except for a small amount of leakage.
common semiconductor manufacturing faults will cause the current to increase by
orders of magnitude, which can be easily detected. This has the advantage of
checking the chip for many possible faults with one measurement.
advantage is that it may catch faults that are not found by conventional
stuck-at fault test vectors. Iddq testing is somewhat more complex than just
measuring the supply current.
If a line
is shorted to Vdd, for example, it will still draw no extra current if the gate
driving the signal is attempting to set it to '1'.
a different vector set that attempts to set the signal to 0 will show a large
increase in quiescent current, signaling a bad part. Typical Iddq test vector
sets may have 20 or so vectors.
Iddq test vectors require only controllability, and not observability. This is
because the observability is through the shared power supply connection. Iddq
testing has many advantages:
§ It is a
simple and direct test that can identify physical defects.
§ The area
and design time overhead are very low.
generation is fast.
application time is fast since the vector sets are small.
catches some defects that other tests, particularly stuck-at logic tests, do
Compared to scan testing, Iddq testing is time consuming, and then more
expensive, since is achieved by current measurements that take much more time
than reading digital pins in mass production.