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Chapter: VLSI Design : CMOS Testing

Text Fixtures

In generic xUnit, a test fixture is all the things that must be in place in order to run a test and expect a particular outcome. Frequently fixtures are created by handling setUp() and tearDown() events of the unit testing framework.



In generic xUnit, a test fixture is all the things that must be in place in order to run a test and expect a particular outcome. Frequently fixtures are created by handling setUp() and tearDown() events of the unit testing framework. In setUp() one would create the expected state for the test, and in tearDown() it would clean up what had been set up.


Four phases of a test:


1.        Set up -- Setting up the test fixture.


2.        Exercise -- Interact with the system under test.


3.        Verify -- Determine whether the expected outcome has been obtained.


4.        Tear down -- Tear down the test fixture to return to the original state. Use of fixtures


Some advantages of fixtures include separation of the test initialization (and destruction) from the testing, reusing a known state for more than one test, and special assumption by the testing framework that the fixture set up works.


1. Design for testability


VLSI designers have a wide variety of CAD tools to choose from, each with their own strengths and weaknesses. The leading Electronic Design Automation (EDA) companies include Cadence, Synopsys, Magma, and Mentor Graphics.


Tanner also offers commercial VLSI design tools. The leading free tools include Electric, Magic, and LASI.


This set of laboratories uses the Cadence and Synopsys tools because they have the largest market share in industry, are capable of handling everything from simple class projects to state-of-the-art integrated circuits.


The full set of tools is extremely expensive but the companies offer academic programs to make the tools available to universities at a much lower cost.


The tools run on Linux and other flavors of UNIX. Setting up and maintaining the tools involves a substantial effort. Once they are setup correctly, the basic tools are easy to use, as this tutorial demonstrates.


Some companies use the Tanner tools because their list price is much lower and they are easy to use. However, their academic pricing is comparable with Cadence and Synopsys, giving little incentive for universities to adopt Tanner.


The Electric VLSI Design System is an open-source chip design program developed by Electric presently does not read the design rules for state-of-the-art nanometer processes and poorly integrates with synthesis and place & route.


Magic is a free Linux-based layout editor with a powerful but awkward interface that was once widely used in universities.


The Layout System for Individuals, LASI, developed by David Boyce, is freely available and runs on Windows. It was last updated in 1999. There are two general strategies for chip design.


Custom design involves specifying how every transistor is connected and physically arranged on the chip.


Synthesized design involves describing the function of a digital chip in a hardware description language such as Verilog or VHDL, then using a computer-aided design tool to automatically generate a set of gates that perform this function, place the gates on the chip, and route the wires to connect the connect the gates.


The majority of commercial designs are synthesized today because synthesis takes less engineering time.


However, custom design gives more insight into how chips are built and into what to do when things go wrong.


Custom design also offers higher performance, lower power, and smaller chip size. The first two labs emphasize the fundamentals of custom design, while the next two use logic synthesis and automatic placement to save time.


2. Tool Setup


These labs assume that you have the Cadence and Synopsys tools installed. The tools generate a bunch of random files. It’s best to keep them in one place. In your home directory,


create some directories by typing:


mkdir IC_CAD


mkdir IC_CAD/cadence


3. Getting Started


Before you start the Cadence tools, change into the cadence directory:cd ~/IC_CAD/cadence Each of our tools has a startup script that sets the appropriate paths to the tools and invokes them.


Start Cadence with the NCSU extensions by running cad-ncsu&A window labeled icfb will open up.


This is the Integrated Circuit Front and Back End (e.g. schematic and layout) software, part of Cadence’s Design Framework interface.


A “What’s New” and a Library Manager window may open up too. Scroll through the icfb window and look at the messages displayed as the tool loads up.


Get in the habit of watching for the messages and recognizing any that are out of the ordinary.


This is very helpful when you encounter problems. All of your designs are stored in a library. If the Library Browser doesn’t open, choose Tools


Library Manager. You’ll use the Library Manager to manipulate your libraries. Don’t try to move libraries around or rename them directly in Linux; there is some funny behavior and you are likely to break them.


Familiarize yourself with the Library Manager. Your cds.lib file includes many libraries from the NCUS CDK supporting the different MOSIS processes. It also includes libraries from the University of Utah.


The File menu allows you to create new libraries and cells within a library, while the Edit menu allows you to copy, rename, delete, and change the access permissions.


Choose the “Attach to existing tech library” and accept the default, UofU AMI 0.60u C5N (3M, 2P, high-res).


This is a technology file for the American Microsystems (now Orbit Semiconductor) 0.6 μm process, containing design rules for layout.


4. Schematic Entry


Our first step is to create a schematic for a 2-input NAND gate. Each gate or larger component is called a cell. Cells have multiple views. The schematic view for a cell built with CMOS transistors will be called cmos sch.


Later, you will build a view called layout specifying how the cell is physically manufactured. In the Library Manager, choose File • New • Cell View… In your lab1_xx library, enter a cell name of nand2 and a view name of cmos_sch. The tool should be Composer - Schematic.


You may get a window asking you to confirm that cmos_sch should be associated with this tool. The schematic editor window will open. Your goal is to draw a gate like the one shown in Figure 1. We are working in a 0.6 μm process with λ = 0.3 μm.


Unfortunately, the University of Utah technology file is configured on a half-lambda grid, so grid units are 0.15 μm. Take care that everything you do is an integer multiple of λ so you don’t come to grief later on. Our NAND gate will use 12 λ (3.6 μm) nMOS and pMOS transistors.


Choose Add • Instance to open a Component Browser window. Choose UofU_Analog_Parts for the library, then select nmos. The Add Instance dialog will open. Set the Width to 3.6u (u indicates microns).


Click in the schematic editor window to drop the transistor. You can click a second time to place another transistor. Return to the Component Browser window and choose pmos. Drop two pMOS transistors.


Then return to the browser and get a gnd and a vdd symbol. When you are in a mode in the editor, you can press ctrl-c or Esc to get out of it.


Other extremely useful commands include Edit • Move, Edit • Copy, Edit • Undo, and Edit

• Delete. Edit • Properties • Object… is also useful to change things like transistor sizes or wire names.


Move the elements around until they are in attractive locations. I like to keep series transistors one grid unit apart and place pMOS transistors two grid units above the nMOS. Look at the bottom of the schematic editor window to see what mode you are in.


Next, use Add • Pin… to create some pins. In the Add Pin dialog, enter a and b. Make sure the direction is “input.”


The tools are case-sensitive, so use lower case everywhere. Place the pins, being sure that a is the bottom one.


Although pin order doesn’t matter logically, it does matter physically and electrically, so you will get errors if you reverse the order. Then place an output pin y. Now, wire the elements together.


Choose Add • Wire (narrow). Click on each component and draw a wire to where it should connect. It is a good idea to make sure every net (wire) in a design has a name.


Otherwise, you’ll have a tough time tracking down a problem later on one of the unnamed nets.


Every net in your schematic is connected to a named pin or to power or ground except the net between the two series nMOS transistors. Choose Add • Wire name… Enter mid or something like that as the name, and click on the wire to name it. Choose Design • Check and Save to save your schematic.


You’ll probably get one warning about a “solder dot on crossover” at the 4-way junction on the output node.


This is annoying because such 4-way junctions are normal and common. Choose Check • Rules Setup… and click on the Physical tab in the dialog. Change Solder On Cross Over from “warning” to “ignored” and close the dialog.


Then Check and Save again and the warning should be gone.


If you have any other warnings, fix them. A common mistake is wires that look like they might touch but don’t actually connect. Delete the wire and redraw it. Poke around the menus and familiarize yourself with the other capabilities of the schematic editor.

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