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Chapter: VLSI Design : CMOS Testing

Logic Verification

Cells are commonly described at three levels of abstraction. The register-transfer level (RTL) description is a Verilog or VHDL file specifying the behavior of the cell in terms of registers and combinational logic.



Cells are commonly described at three levels of abstraction. The register-transfer level (RTL) description is a Verilog or VHDL file specifying the behavior of the cell in terms of registers and combinational logic.


It often serves as the specification of what the chip should do. The schematic illustrates how the cell is composed from transistors or other cells. The layout shows how the transistors or cells are physically arranged.


Logic verification involves proving that the cells perform the correct function. One way to do this is to simulate the cell and apply a set of 1’s and 0’s called test vectors to the inputs, then check that the outputs match expectation.


Typically, logic verification is done first on the RTL to check that the specification is correct. A testbench written in Verilog or VHDL automates the process of applying and checking all of the vectors.


The same test vectors are then applied to the schematic to check that the schematic matches the RTL.


Later, we will use a layout-versus schematic (LVS) tool to check that the layout matches the schematic (and, by inference, the RTL).


You will begin by simulating an RTL description of the NAND gate to become familiar with reading RTL and understanding a testbench. In this tutorial, the RTL and testbench are written in System Verilog, which is a 2005 update to the popular Verilog hardware description language.


There are many Verilog simulators on the market, including NC-Verilog from Cadence, VCS from Synopsys, and ModelSim from Mentor Graphics.


This tutorial describes how to use NC Verilog because it integrates gracefully with the other Cadence tools.


NCVerilog compiles your Verilog into an executable program and runs it directly, making it much faster than the older interpreted simulators. Make a new directory for simulation (e.g. nand2sim).

Copy nand2.sv, nand2.tv, and testfixture.verilog from the course directory into your new directory.


mkdir nand2sim cd nand2sim


cp /courses/e158/10/nand2.sv . cp /courses/e158/10/nand2.tv .


cp /courses/e158/10/nand2.testfixture testfixture.verilog


nand2.sv is the SystemVerilog RTL file, which includes a behavioral description of a nand2 module and a simple self-checking testbench that includes testfixture.verilog. testfixture.verilog reads in testvectors from nand2.tv and applies them to pins of the nand2 module.


After each cycle it compares the output of the nand2 module to the expected output, and prints an error if they do not match.


Look over each of these files and understand how they work. First, you will simulate the nand2 RTL to practice the process and ensure that the testbench works.


Later, you will replace the behavioral nand2 module with one generated from your Electric schematic and will resimulate to check that your schematic performs the correct function.


At the command line, type sim-nc nand2.sv to invoke the simulator. You should see some messages ending with


ncsim> run


Completed 4 tests with 0 errors.


Simulation stopped via $stop(1) at time 81 NS + 0


You’ll be left at the ncsim command prompt. Type quit to finish the simulation. If the simulation hadn’t run correctly, it would be helpful to be able to view the results.


NC-Verilog has a graphical user interface called SimVision. The GUI takes a few seconds to load, so you may prefer to run it only when you need to debug.


To rerun the simulation with the GUI, type sim-ncg nand2.sv A Console and Design Browser window will pop up.


In the browser, click on the + symbol beside the testbench to expand, then click on dut. The three signals, a, b, and y, will appear in the pane to the right. Select all three, then right-click and choose Send to Waveform Window.


In the Waveform Window, choose Simulation • Run. You’ll see the waveforms of your simulation; inspect them to ensure they are correct. The 0 errors message should also appear in the console.


If you needed to change something in your code or testbench or test vectors, or wanted to add other signals, do so and then Simulation • Reinvoke Simulator to recompile everything and bring you back to the start.


Then choose Run again. Make a habit of looking at the messages in the console window and learning what is normal.


Warnings and errors should be taken seriously; they usually indicate real problems that will catch you later if you don’t fix them.


1. Schematic Simulation


Next, you will verify your schematic by generating a Verilog deck and pasting it into the RTL Verilog file.


While viewing your schematic, click on Tools • Simulation • NCVerilog to open a window for the Verilog environment. Note the run directory (e.g. nand2_run1), and press the button in the upper left to initialize the design.


Then press the next button to generate a netlist. Look in the icfb window for errors and correct them if necessary.


You should see that the pmos, nmos, and nand2 cells were all netlisted. In your Linux terminal window, cd into the directory that was created. You’ll find quite a few files.


The most important are verilog.inpfiles, testfixture.template, and testfixture.verilog. Each cell is netlisted into a different directory under ihnl. verilog.inpfiles states where they are.


Take a look at the netlist and other files. testfixture.template is the top level module that instantiates the device under test and invokes the testfixture.verilog.


Copy your from your nand2sim directory to your nand2_run1 directory using a command such as

cp ../nand2sim/testfixture.verilog .cp ../nand2sim/nand2.tv .


Back in the Virtuoso Verilog Environment window, you may wish to choose Setup • Record Signals.


Click on the “All” button to record signals at all levels of the hierarchy. (This isn’t important for the nand with only one level of hierarchy, but will be helpful later.)


Then  choose Setup • Simulation. Change the Simulation Log File to indicate simout.tmp


–sv. This will print the results in simout.tmp.


The –sv flag indicates that the simulator should accept SystemVerilog syntax used in the testfixture.verilog. Set the Simulator mode to “Batch” and click on the Simulate button.


You should get a message that the batch simulation succeeded.This doesn’t mean that it is correct, merely that it run.


In the terminal window, view the simout.tmp file. It will give some statistics about the compilation, then should indicate that the 4 tests were completed with 0 errors.


If the simulation fails, the simout.tmp file will have clues about the problems. Change the simulator mode to Interactive to rerun with the GUI.

Be patient; the GUI takes several seconds to start and gives no sign of life until then. Add the waveforms again and run the simulation.


You may need to zoom to fit all the waves. For some reason, SimVision doesn’t print the $display message about the simulation succeeding with no errors.


You will have to read the simout.tmp file at the command line to verify that the test vectors passed. If you find any logic errors, correct the schematic and resimulate.

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