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Chapter: VLSI Design : CMOS Testing

Silicon Debug Principal

The rapid pace of innovation has created powerful SOC solutions at consumer prices.



The rapid pace of innovation has created powerful SOC solutions at consumer prices.


This has created a highly competitive market place where billions of dollars can be won by the right design delivered at the right time.


These new designs are produced on processes that challenge the fundamental law of physics and are highly sensitive to equipment variation.


The industry now produces new designs in a complex world where process and design interaction have created new complex failures that stand in the way of billion-dollar opportunities.


These interactions lead to new types of defects such as blocked chains, which create noise in the debug/diagnosis process.


They also lead to new types of design issues such as delay defects in combinational and sequential logic.


The challenge is made even greater by the growing complexity in device structure and design techniques.


Multiple design organizations use multiple IP blocks and multiple libraries that need to work Together throughout the process window, often across multiple fabs.


These new challenges come at a time when product lifetimes are shrinking, leading to pressure to reduce time for debug and characterization activities. These problems are seen for the first time at first silicon.


Test the first chips back from fabrication If you are lucky, they work the first time If not Logic bugs vs. electrical failures Most chip failures are logic bugs from inadequate simulation or verification Some are electrical failures Crosstalk Dynamic nodes: leakage, charge sharing Ratio failures A few are tool or methodology failures (e.g. DRC) Fix the bugs and fabricate a corrected chip Silicon debug (or “bringup”) is primarily a Non-Recurring Engineering (NRE) cost (like design) Contrast this with manufacturing test which has to be applied to every part shipped.


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