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Important Short Questions and Answers: Embedded Systems - Memory and Input/Output Management

Embedded Systems - Important Short Questions and Answers: Embedded Systems - Memory and Input/Output Management



1. What are Data registers in I/O devices?


Data registers hold values that are treated as data by the device, such as the data read or written by a disk.


2. What are Status registers in I/O devices?


Status registers provide information about the device’s operation, such as whether the current transaction has completed.


3. What is baud rate?


The data bits are sent as high and low voltages at a uniform rate. This uniform rate at which data bits are sent or received is known as baud rate.


4. What is I/O -mapped I/O and memory-mapped I/O?


I/O mapped I/O uses separate I/O instructions for I/O programming and a separate address space is provided for I/O operations. Memory-mapped I/O uses the same address space used by CPU instructions for the registers in each I/O device and Programs use the CPU’s normal read and write instructions to communicate with the devices.


5. What is polling?


Checking an I/O device whether it is finished its ready by reading its status register is often called polling.


6. Define Interrupt.


An Interrupt is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change in execution. A hardware interrupt causes the processor to save its state of execution and begin execution of a handler. Software interrupts are usually implemented as instructions in the instruction set, which cause a context switch to an interrupt handler similar to a hardware interrupt. Interrupts are a commonly used technique for computer multitasking, especially in real-time computing. Such a system is said to be interrupt-driven.


7. What are interrupt priorities and vectors?


Interrupt priorities allow the CPU to recognize some interrupts as more important than others, and interrupt vectors allow the interrupting device to specify its handler.


8. What is interrupt Masking?


The priority mechanism must ensure that a lower-priority interrupt does not occur when a higher-priority interrupt is being handled. The decision process is known as masking.


9. What do you mean by a non-maskable interrupt?

The highest-priority interrupt is normally called the non-maskable interrupt (NMI).


10. What is ISR?


An interrupt handler, also known as an interrupt service routine (ISR), is a callback subroutine in an operating system or device driver whose execution is triggered by the reception of an interrupt used for servicing an interrupt.


11. What is a cache memory?


A cache is a small, fast memory that holds copies of some of the contents of main memory. Because the cache is fast, it provides higher-speed access for the CPU; but since it is small, not all requests can be satisfied by the cache, forcing the system to wait for the slower main memory. Caching makes sense when the CPU is using only a relatively small set of memory locations at any one time; the set of active locations is often called the working set.


12. What is a cache controller?


A cache controller mediates between the CPU and the memory system comprised of the main memory. The cache controller sends a memory request to the cache and main memory. If the requested location is in the cache, the cache controller forwards the location’s contents to the CPU and aborts the main memory request. If the location is not in the cache, the controller waits for the value from main memory and forwards it to the CPU.


13. What do you mean by a cache hit and a miss?


If the requested location is found in the cache memory this is called a cache it. If it is not found in the cache the request is forwarded to the main memory, this is called a cache miss.


14. What are the types of cache misses?

Compulsory miss, capacity miss and conflict miss


15. What is compulsory cache miss?

A compulsory miss also known as a cold miss occurs the first time a location is used.


16. What is capacity cache miss?

A capacity miss is caused by a too large working set.


17. What is conflict cache miss?

A conflict miss happens when two locations map to the same location in the cache.


18. What is write-through and write-back?


In write-through policy every write changes both the cache and the corresponding main memory location. This scheme ensures that the cache and main memory are consistent, but may generate some additional main memory traffic. We can reduce the number of times we write to main memory by using a write-back policy. If we write only when we remove a location from the cache, we eliminate the writes when a location is written several times before it is removed from the cache.


This is known as write-back policy.



19. What is a page fault?


When the CPU requests an address that is not in main memory, the Memory Management Unit generates an exception called a page fault.


20. What is a TLB?


The efficiency of paged address translation may be increased by caching page translation information. A cache for address translation is known as a translation look aside buffer (TLB).

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