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Digital signal processors
Signal processors started out as special processors that were designed for implementing digital signal processing (DSP) algo-rithms. A good example of a DSP function is the finite impulse response (FIR) filter. This involves setting up two tables, one containing sampled data and the other filter coefficients that determine the filter response. The program then performs a series of repeated multiply and accumulates using values from the tables. The bandwidth of such filters depends on the speed of these simple operations. With a general-purpose architecture like the M68000 family the code structure would involve setting up two tables in external memory, with an address register allocated to each one to act as a pointer. The beginning and the end of the code would consist of the loop initialisation and control, leaving the multiply–accumulate operations for the central part. The M68000 instruction set does offer some facilities for efficient code: the incremental addressing allows pointers to progress down the tables automatically, and the decrement and branch instruction provides a good way of implementing the loop structures. How-ever, the disadvantages are many: the multiply takes >40 clocks, the single bus is used for all the instruction fetches and table searches, thus consuming time and bandwidth. In addition the loop control timings vary depending on whether the branch is taken or not. This can make bandwidth predictions difficult to calculate. This results in very low bandwidths and is therefore of limited use within digital signal processing. This does not mean that an MC68000 cannot perform such functions: it can, providing performance is not of an issue.
RISC architectures like the PowerPC family can offer some immediate improvements. The capability to perform single cycle arithmetic is an obvious advantage. The Harvard architecture reduces the execution time further by allowing simultaneous data and instruction fetches. The PowerPC can, by virtue of its high performance, achieve performances suitable for many DSP appli-cations. The system cost is high involving a multiple chip solution with very fast memory etc. In applications that need high speed general processing as well, it can also be a suitable solution. The ARM 9E processor with its DSP enhanced instructions (essentially speeded up multiply instructions) can also provide DSP levels of performance without the need of a DSP.
Another approach is to build a dedicated processor to perform certain algorithms. By using discrete building blocks, such as hardware multipliers, counters etc., a total hardware solution can be designed to perform such functions. Modulo counters can be used to form the loop structures and so on. The disadvantages are cost and a loss of flexibility. Such hardware solutions are difficult to alter or program. What is obviously required is a processor whose architecture is enhanced specifically for DSP applications.
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