With the ability of semiconductor manufacturers to be able to integrate several million transistors onto a single piece of silicon, it should come as no surprise that there are now processors available which take the idea of integration offered by a microcontroller, but use a high performance processor instead. The Intel 80186 started this process by combining DMA channels with an 8086 architecture. The most successful family so far has been the MC683xx family from Motorola. There are now several members of the family currently available.
They combine an M68000 or MC68020 (CPU32) family processor and its asynchronous memory interface, with all the standard interface logic of chip selects, wait state generators, bus and watchdog timers into a system interface module and use a second RISC type processor to handle specific I/O functions. This approach means that all the additional peripherals and logic needed to construct an MC68000- based system has gone. In many cases, the hardware design is almost at the ‘join up the dots’ level where the dots are the processor and memory pins.
This approach has been adopted by others and many differ-ent processor cores, such as SPARC and MIPs, are now available in similar integrated processors. PowerPC versions of the MC68360 are now in production where the MC68000-based CPU32 core is replaced with a 50 MHz PowerPC processor. For embedded systems, this is definitely the way of the future.
The MC68302 uses a 16 MHz MC68000 processor core with power down modes and either an 8 or 16 bit external bus. The system interface block contains 1152 bytes of dual port RAM, 28 pins of parallel I/O, an interrupt controller and a DMA device, as well as the standard glue logic. The communications processor is a RISC machine that controls three multiprotocol channels, each with their own pair of DMA channels. The channels support BISYNC, DDCMP, V.110, HDLC synchronous modes and stand-ard UART functions. This processor takes buffer structures from either the internal or external RAM and takes care of the day-to-day activities of the serial channels. It programs the DMA channel to transfer the data, performs the character and address compari-sons and cyclic redundancy check (CRC) generation and check-ing. The processor has sufficient power to cope with a combined data rate of 2 Mbits per second across the three channels. Assum-ing an 8 bit character and a single interrupt to poll all three channels, the processor is handling the equivalent of an interrupt every 12 microseconds. In addition, it is performing all the data framing etc. While this is going on, the on-chip M68000 is free to perform other functions, like the higher layers of X.25 or other OSI protocols as shown.
The MC68332 is similar to the MC68302, except that it has a CPU32 processor (MC68020-based) running at 16 MHz and a timer processor unit instead of a communications processor. This has 16 channels which are controlled by a RISC-like processor to perform virtually any timing function. The timing resolution is down to 250 nanoseconds with an external clock source or 500 nanoseconds with an internal one. The timer processor can per-form the common timer algorithms on any of the 16 channels without placing any overhead on the CPU32.
A queued serial channel and 2 kbits of power down static RAM are also on-chip and for many applications, all that is required to complete a working system is an external program EPROM and a clock.
This is a trend that many other architectures are following especially with RISC processors. Apart from the high performance range of the processor market or where complete flexibility is needed, most processors today come with at least some basic peripherals such as serial and parallel ports and a simple or glueless interface to memory. In many cases, they dramatically reduce the amount of hardware design needed to add external memory and thus complete a simple design. This type of processor is gaining popularity with designers.