M6800 synchronous bus - interfaces
Support for the M6800 synchronous bus initially offered early M68000
system designers access to the M6800 peripherals and allowed them to build
designs as soon as the processor was available. With today’s range of
peripherals with specific M68000 interfaces, this interface is less used.
However, the M6800 parts are now extremely inexpensive and are often used in
The additional signals involved are the E clock, valid memory address
(VMA*) and valid peripheral address (VPA*). The cycle starts in a similar way
to the M68000 asynchronous interface except that DTACK* is not returned. The
address decoding gener-ates a peripheral chip select which asserts VPA*. This
tells the M68000 that a synchronous cycle is being performed.
The address decoding monitors the E clock signal, which is derived from
the main system clock, but is divided down by 10 with a 6:4 mark/space ratio.
It is not referenced from any other signal and is free running. At the
appropriate time (i.e. when E goes low) VMA* is asserted. The peripheral waits
for E to go high and transfers the data. When E goes low, the processor negates
VMA* and the address and data strobes to end the cycle.
For systems running at 10 MHz or lower, standard 1 MHz M6800 parts can
be used. For higher speeds, 1.5 or 2 MHz versions must be employed. However,
higher speed parts running at a lower clock frequency will not perform the
peripheral functions at full performance.