A memory’s organisation refers to how the data is arranged within the memory chips and within the array of chips that is used to form the system memory. An individual memory’s storage is measured in bits but can be organised in several different ways. A 1 Mbit memory can be available as a 1 Mbit × 1 device, where there is only a single data line and eight are needed in parallel to store one byte of data. Alternatives are the 256 kbits × 4, where there are four data lines and only two are needed to store a byte, and 128 kbit × 8, which has 8 data lines. The importance of these different organisations becomes apparent when upgrading memory and determining how many chips are needed.
The minimum number of chips that can be used is deter-mined by the width of the data path from the processor and the number of data lines the memory chip has. For an MC68000 processor with a 16 bit wide data path, 16 × 1 devices, 4 × 4 or 2 × 8 devices would be needed. For a 32 bit processor, like the MC68020, MC68030, MC68040, 80386DX or 80486, this figure doubles. What is interesting is that the wider the individual memory chip’s data storage, the smaller the number of chips that is required to upgrade. This does not mean that, for a given amount of memory, less × 4 and × 8 chips are needed when compared with × 1 devices, but that each minimum upgrade can be smaller, use fewer chips and be less expensive. With a 32 bit processor and using 1 Mbit × 1 devices, the minimum upgrade would need 32 chips and add 32 Mbytes. With a × 4 device, the minimum upgrade would only need 8 chips and add 8 Mbytes.
This is becoming a major problem as memories become denser and the smaller size chips are discontinued. This poses problems to designers that need to design some level of upgrade capability to cater for the possible — some would say inevitable — need for more memory to store the software. With the smallest DRAM chip that is still in production being a 16 Mbit device and the likelihood that this will be replaced by 64 and 128 Mbit devices in the not so distant future, the need for one additional byte could result in the addition of 8 or 16 Mbytes or memory. More impor-tantly, if a × 1 organisation is used, then this means that an additional 8 chips are needed. By using a wider organisation, the number of chips is reduced. This is becoming a major issue and is placing a lot of pressure on designers to keep the memory budget under control. The cost of going over is becoming more and more expensive. With cheap memory, this could be argued as not being an issue but there is still the space and additional cost. Even a few cents multiplied by large production volumes can lead to large increases.
By 1 organisation
Today, single-bit memories are not as useful as they used to be and their use is in decline compared to wider data path devices. Their use is restricted to applications that need non-standard width memory arrays that these type of machines use, e.g. 12 bit, 17 bit etc. They are still used to provide a parity bit and can be found on SIMM memory modules but as systems move away from implementing parity memory — many PC motherboards no longer do so — the need for such devices will decline.
By 4 organisation
This configuration has effectively replaced the × 1 memory in microprocessor applications because of its reduced address bus loading and complexity — only 8 chips are needed to build a 32 bit wide data path instead of 32 and only two are needed for an 8 bit wide bus.
By 8 and by 9 organisations
Wider memories such as the × 8 and × 9 are beginning to replace the × 4 parts in many applications. Apart from higher integration, there are further reductions in address bus capaci-tance to build a 32 or 64 bit wide memory array. The reduction in bus loading can improve the overall access time by greatly reduc-ing the address setup and stabilisation time, thus allowing more time within the memory cycle to access the data from the memo-ries. This improvement can either reduce costs by using slower and cheaper memory, or allow a system to run faster given a specific memory part. The × 9 variant provides a ninth bit for parity protection. For microcontrollers, these parts allow memory to be increased in smaller increments.
By 16 and greater organisations
Wider memories with support for 16 bits or wider memory are already appearing but it is likely that they will integrate more of the interface logic so that the time consumed by latches and buffers during the memory access will be removed, thus allowing slower parts to be used in wait state-free designs.