Unified versus Harvard caches
There is another aspect of cache design that causes great debate among designers and this concerns whether the cache is unified or separate. A unified cache, as used on the Intel 80486DX processors and the Motorola MPC601 PowerPC chip, uses the same cache mechanism to store both data and instructions. The separate or Harvard cache architecture has separate caches for data and instructions. The argument for the unified cache is that its single set of tags and comparators reduces the amount of silicon needed to implement it and thus for a given die area, a larger cache can be provided compared to separate caches. The argument against is that a unified cache usually has only a single port and therefore simultaneous access to both instructions and data will result in one or the other being delayed while the first access is completed. This delay can halt or slow down the processor’s ability to execute instructions.
Conversely, the Harvard approach uses more silicon area for the second set of tags and comparators but does allow simul-taneous access. In reality, the overall merits of each approach depend on several factors, and depending where the cross-over points lie, the factors will be in favour of one or other. If software needs to exploit superscalar operation then the Harvard architec-ture is less likely to impede superscalar execution. If the applica-tion has large data and code structures, then a larger unified cache may be better. As with most cache organisation decisions, the only clear way to make a decision is to evaluate using the end applica-tion and the test software.