As well as different sizes and organisations, memory chips have different access times. The access time is the maximum time taken by the chip to read or write data and it is important to match the access time to the design. (It usually forms part of the part number: MCM51000AP10 would be a 100 ns access time memory and MCM51000AP80 would be an 80 ns version.) If the chip is too slow, the data that the processor sees will be invalid and corrupt, resulting in software problems and crashes. Some designs allow memories of different speed to be used by inserting wait states between the processor and memory so that sufficient time is given to allow the correct data to be obtained. These often require jumper settings to be changed or special setup software to be run, and depend on the manufacture and design of the board.
If a processor clock speed is increased, the maximum memory access time must be reduced — so changing to a faster processor may require these settings to be modified. This is becoming less of a problem with the advent of decoupled proces-sors where the CPU speed can be set as a ratio of the bus speed and by changing an initialisation routine, a faster CPU can be used with the same external bus as a slower one. This is similar to the overdrive processors that clock the internal CPU either 22 or 4 times faster. They are using the same trick except that there is no additional software change needed.