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Direct memory access (DMA) controllers are frequently an elegant hardware solution to a recurring software/system prob-lem of providing an efficient method of transferring data from a peripheral to memory.
In systems without DMA, the solution is to use the proces-sor to either regularly poll the peripheral to see if it needs servicing or to wait for an interrupt to do so. The problem with these two methods is that they are not very efficient. Polling, by its very nature, is going to check the status and find that no action is required more times than it will find that servicing is needed. If this is not the case, then data can be lost through data over- and under-run. This means that it spends a lot of time in non-construc-tive work. In many embedded systems, this is not a problem but in low power systems, for example, this unnecessary work process-ing and power consumption cannot be tolerated.
Interrupts are a far better solution. An interrupt is sent from the peripheral to the processor to request servicing. In many cases, all that is needed is to simply empty or load a buffer. This solution starts becoming an issue as the servicing rate increases. With high speed ports, the cost of interrupting the processor can be higher than the couple of instructions that it executes to empty a buffer. In these cases, the limiting factor for the data transfer is the time to recognise, process and return from the interrupt. If the data needs to be processed on a byte by byte basis in real-time, this may have to be tolerated but with high speed transfers this is often not the case as the data is treated in packets.
This is where the DMA controller comes into its own. It is a device that can initiate and control bus accesses between I/O devices and memory, and between two memory areas. With this type of facility, the DMA controller acts as a hardware implemen-tation of the low-level buffer filling or emptying interrupt routine.
There are essentially three types of DMA controller which offer different levels of sophistication concerning memory ad-dress generation. They are often classified in terms of their ad-dressing capability into 1D, 2D and 3D types. A 1D controller would only have a single address register, a 2D device two and a 3D device three or more.
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