I/O Port Configuration
of 8051 has bidirectional capability. Port 0 is called 'true bidirectional
port' as it floats (tristated) when configured as input. Port-1, 2, 3 are
called 'quasi bidirectional port'. Port-0 Pin Structure
has 8 pins (P0.0-P0.7).
structure of a Port-0 pin is shown in fig 4.10.
can be configured as a normal bidirectional I/O port or it can be used for
address/data interfacing for accessing external memory. When control is '1',
the port is used for address/data interfacing. When the control is '0', the
port can be used as a normal bidirectional I/O port.
assume that control is '0'. When the port is used as an input port, '1' is
written to the latch. In this situation both the output MOSFETs are 'off'.
Hence the output pin floats. This high impedance pin can be pulled up or low by
an external source. When the port is used as an output port, a '1' written to
the latch again turns 'off' both the output MOSFETs and causes the output pin
to float. An external pull-up is required to output a '1'. But when '0' is
written to the latch, the pin is pulled down by the lower MOSFET. Hence the
output becomes zero.
control is '1', address/data bus controls the output driver MOSFETs. If the
address/data bus (internal) is '0', the upper MOSFET is 'off' and the lower
MOSFET is 'on'. The output becomes '0'. If the address/data bus is '1', the
upper transistor is 'on' and the lower transistor is 'off'. Hence the output is
'1'. Hence for normal address/data interfacing (for external memory access) no
pull-up resistors are required.
latch is written to with 1's when used for external memory access. Port-1 Pin
has 8 pins (P1.1-P1.7) .The structure of a port-1 pin is shown in fig 4.11.
does not have any alternate function i.e. it is dedicated solely for I/O
interfacing. When used as output port, the pin is pulled up or down through
internal pull-up. To use port-1 as input port, '1' has to be written to the
latch. In this input mode when '1' is written to the pin by the external device
then it read fine. But when '0' is written to the pin by the external device
then the external source must sink current due to internal pull-up. If the
external device is not able to sink the current the pin voltage may rise,
leading to a possible wrong reading.
has 8-pins (P2.0-P2.7) . The structure of a port-2 pin is shown in fig 4.12.
used for higher external address byte or a normal input/output port. The I/O
operation is similar to Port-1. Port-2 latch remains stable when Port-2 pin are
used for external memory access. Here again due to internal pull-up there is
limited current driving capability.
has 8 pin (P3.0-P3.7) . Port-3 pins have alternate functions. The structure of
a port-3 pin is shown in fig 4.13.
of Port-3 can be individually programmed for I/O operation or for alternate
function. The alternate function can be activated only if the corresponding
latch has been written to '1'. To use the port as input port, '1' should be
written to the latch. This port also has internal pull-up and limited current
functions of Port-3 pins are –
1. Port 1,
2, 3 each can drive 4 LS TTL inputs.
can drive 8 LS TTL inputs in address /data mode. For digital output port, it
needs external pull-up resistors.
3 pins can also be driven by open-collector or open-drain outputs.
4. Each Port
3 bit can be configured either as a normal I/O or as a special function bit.
a subtle difference between reading a latch and reading the output port pin.
status of the output port pin is sometimes dependant on the connected load. For
instance if a port is configured as an output port and a '1' is written to the
latch, the output pin should also show '1'. If the output is used to drive the
base of a transistor, the transistor turns 'on'.
If the port
pin is read, the value will be '0' which is corresponding to the base-emitter
voltage of the transistor.
Reading a latch: Usually the instructions that
read the latch, read a value, possibly change it, and then rewrite it to the latch. These are called
"read-modify-write" instructions. Examples of a few instructions are-
A; P2 <-- P2 or A
C; Move carry bit to PX.Y bit.
the latch value of P2 is read, is modified such that P2.1 is the same as Carry
and is then written back to P2 latch.
Reading a Pin: Examples of a few instructions
that read port pin, are-
MOV A, P0
; Move port-0 pin values to A
P1; Move port-1 pin values to A
external program memory, always 16 bit address is used. For example - MOVC A, @
MOVC A, @
external data memory can be either 8-bit address or 16-bit address - 8-bit
address- MOVX A, @Rp where Rp is either R0 or R1
address- MOVX A,@DPTR
external memory access in 8051 can be shown by a schematic diagram as given in
8-bit external address is used for data memory (i.e. MOVX @Rp) then the content
of Port-2 SFR remains at Port-2 pins throughout the external memory cycle. This
facilitates memory paging as the upper 8 bit address remains fixed.
any access to external memory, the CPU writes FFH to Port-0 latch (SFR). If the
user writes to Port-0 during an external memory fetch, the incoming byte is
corrupted. External program memory is accessed under the following condition.
typical use of code/program memory access:
program memory can be not only used to store the code, but also for lookup
table of various functions required for a particular application. Mathematical
functions such as Sine, Square root, Exponential, etc. can be stored in the
program memory (Internal or eternal) and these functions can be accessed using
two 16-bit programmable UP timers/counters. They can be configured to operate
either as timers or as event counters. The names of the two counters are T0 and
T1 respectively. The timer content is available in four 8-bit special function
registers, viz, TL0,TH0,TL1 and TH1 respectively.
"timer" function mode, the counter is incremented in every machine
cycle. Thus, one can think of it as counting machine cycles. Hence the clock
rate is 1/12 th of the oscillator frequency.
"counter" function mode, the register is incremented in response to a
1 to 0 transition at its corresponding external input pin (T0 or T1). It
requires 2 machine cycles to detect a high to low transition. Hence maximum
count rate is 1/24 th of oscillator frequency.
operation of the timers/counters is controlled by two special function
registers, TMOD and TCON respectively.
Mode control (TMOD) Special Function Register:
register is not bit addressable.
bits of TMOD are described as follows -
M1 and M0
are mode select bits.
Counter control logic:
Timer/Counter Control Logic Timer control (TCON) Special function register:
bit addressable. The address of TCON is 88H. It is partly related to Timer and
partly to interrupt.
various bits of TCON are as follows.
Timer1 overflow flag. It is set when timer rolls from all 1s to 0s. It is
cleared when processor vectors to execute ISR located at address 001BH.
Timer1 run control bit. Set to 1 to start the timer / counter. TF0 : Timer0
overflow flag. (Similar to TF1)
TR0 : Timer0
run control bit.
Interrupt1 edge flag. Set by hardware when an external interrupt edge is
detected. It is cleared when interrupt is processed.
Interrupt0 edge flag. (Similar to IE1)
Interrupt1 type control bit. Set/ cleared by software to specify falling edge /
low level triggered external interrupt.
Interrupt0 type control bit. (Similar to IT1)
mentioned earlier, Timers can operate in four different modes. They are as
follows Timer Mode-0:
mode, the timer is used as a 13-bit UP counter as follows.
Mode-2: (Auto-Reload Mode)
This is a
8 bit counter/timer operation. Counting is performed in TLX while THX stores a
constant value. In this mode when the timer overflows i.e. TLX becomes FFH, it
is fed with the value stored in THX. For example if we load THX with 50H then
the timer in mode 2 will count from 50H to FFH. After that 50H is again
reloaded. This mode is useful in applications like fixed time sampling.
in mode-3 simply holds its count. The effect is same as setting TR1=0. Timer0
in mode-3 establishes TL0 and TH0 as two separate counters.
bits TR1 and TF1 are used by Timer-0 (higher 8 bits) (TH0) in Mode-3 while TR0
and TF0 are available to Timer-0 lower 8 bits(TL0).