I/O Ports and Data Transfer Concepts

I/O Ports

There are two methods in which I/O devices can be connected to the Microprocessor.

ü Memory mapped I/O

ü I/O mapped I/O

Memory mapped I/O:

In this method I/O device is treated like the memory. Here there is no IO/M signal. If the processor wants to read the data from a I/O device it will place the address of the I/O device on the address bus. Then the I/O device will get selected. The memory which is having the same address will also get selected.so we have to use separate address for memory and separate address for I/O device.

I/O mapped I/O:

Here we have the IO/M signal. So we can select either the memory or I/O device for read and write operation.

Data Transfer Concepts

ü Parallel data transfer

ü Serial data transfer

I.  Parallel data transfer

ü Programmed I/O

ü Interrupt I/O

ü DMA

Programmed I/O:

Here the processor has to check whether the I/O device is ready or not through the Ready signal of the I/O device. If the ready signal is high then it will send the data to the I/O device. Otherwise it will continuously check the Ready signal. The processor is busy in checking the Ready signal. The drawback is wastage of time.

Interrupt I/O:

In this method the I/O device will interrupt the Processor through the INTR signal to indicate to the processor that it is ready to accept the next data. Then the processor will send the INTA signal. Then the processor stops its normal execution and start transferring the data to the I/O device.

DMA:

Using DMA I/O device can directly transfer the data to the Memory using the Address and Data buses of Processor.

II. Serial data Transfer

Some of the external I/0 devices receive only the serial data. Normally serial communication is used in the MultiProcessor environment. 8051 has two pins for serial communication.

ü SID- Serial Input data.

ü SOD-Serial Output data.

Interrupts

The processor has the following interrupts:

INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI instructions or using more complicated method of updating the FLAGS register with the help of the POPF instruction.

When an interrupt occurs, the processor stores FLAGS register into stack, disables further interrupts, fetches from the bus one byte representing interrupt type, and jumps to interrupt processing routine address of which is stored in location 4 * <interrupt type>. Interrupt processing routine should return with the IRET instruction.

NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is stored in location 0008h. This interrupt has higher priority then the maskable interrupt.

Software interrupts can be caused by:

ü INT instruction - breakpoint interrupt. This is a type 3 interrupt.

ü INT <interrupt number> instruction - any one interrupt from available 256 interrupts.

ü INTO instruction - interrupt on overflow

ü Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the CPU processes this interrupt it clears TF flag before calling the interrupt processing routine.

Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape opcode (type 7).