HDL For Sequential Circuits

HDL FOR SEQUENTIAL CIRCUITS

1. Behavioral Modeling

//Behavioral description of 4-to-1 line mux

module mux4x1_bh (i0,i1,i2,i3,select,y);

input i0,i1,i2,i3; input [1:0] select; output y;

reg y;

always @(i0 or i1 or i2 or i3 or select)

case (select) 2'b00: y = i0; 2'b01: y = i1; 2'b10: y = i2; 2'b11: y = i3;

endcase endmodule

w      In 4-to-1 line multiplexer, the select input is defined as a 2-bit vector and output y is declared as a reg data.

w      The always block has a sequential block enclosed between the keywords case and endcase.

w      The block is executed whenever any of the inputs listed after the @ symbol changes in value.

w      A test bench is an HDL program used for applying stimulus to an HDL design in order to test it and observe its response during simulation.

w      In addition to the always statement, test benches use the initial statement to provide a stimulus to the circuit under test.

w      The always statement executes repeatedly in a loop. The initial statement executes only once starting from simulation time=0 and may continue with any operations that are delayed by a given number of units as specified by the symbol #.

2. Descriptions of Circuits

w      Structural Description – This is directly equivalent to the schematic of a circuit and is specifically oriented to describing hardware structures using the components of a circuit.

w      Dataflow Description – This describes a circuit in terms of function rather than structure and is made up of concurrent assignment statements or their equivalent. Concurrent assignments statements are executed concurrently, i.e. in parallel whenever one of the values on the right hand side of the statement changes.

w      Hierarchical Description – Descriptions that represent circuits using hierarchy have multiple entities, one for each element of the Hierarchy.

w      Behavioral Description – This refers to a description of a circuit at a level higher than the logic level. This type of description is also referred to as the register transfers level.

3. Flip-Flops and Latches

module D_latch(Q,D,control);

output Q;

input D,control;

reg Q;

always @(control or D)

if(control) Q = D; //Same as: if(control=1) endmodule

//T flip-flop from D flip-flop and gates

module TFF (Q,T,CLK,RST);

output Q;

input T,CLK,RST; wire DT;

assign DT = Q ^ T ; //Instantiate the D flip-flop

DFF TF1 (Q,DT,CLK,RST); endmodule

//JK flip-flop from D flip-flop and gates

module JKFF (Q,J,K,CLK,RST);

output Q;

input J,K,CLK,RST; wire JK;

assign JK = (J & ~Q) | (~K & Q);

//Instantiate D flipflop

DFF JK1 (Q,JK,CLK,RST);

Endmodule