Counters

COUNTERS

•          Counters are a specific type of sequential circuit.

•          Like registers, the state, or the flip-flop values themselves, serves as the “output.”

•          The output value increases by one on each clock cycle.

•          After the largest value, the output “wraps around” back to 0.

1. Benefits of counters

•          Counters can act as simple clocks to keep track of “time.”

•          You may need to record how many times something has happened.

–   How many bits have been sent or received?

–   How many steps have been performed in some computation?

•          All processors contain a program counter, or PC.

– Programs consist of a list of instructions that are to be executed one after another (for the most part).

–   The PC keeps track of the instruction currently being executed.

– The PC increments once on each clock cycle, and the next program instruction is then executed.

2. Design Example: Synchronous BCD Counter

·              Use the sequential logic model to design a synchronous BCD counter with D flip-flops

·              State Table =>

·              Input combinations 1010 through 1111 are don’t cares

·              Use K-Maps to two-level optimize the next state equations and manipulate into forms containing XOR gates:

·              The logic diagram can be draw from these equations

3. COUNTER TYPES

Asynchronous Counter (Ripple or Serial Counter)

Each FF is triggered one at a time with output of one FF serving as clock input of next FF in the chain.

Synchronous Counter (a.k.a. Parallel Counter)

All the FF’s in the counter are clocked at the same time.

Up Counter

Counter counts from zero to a maximum count.

Down Counter

Counter counts from a maximum count down to zero.

BCD Counter

Counter counts from 0000 to 1001 before it recycles.

Pre-settable Counter

Counter that can be preset to any starting count either synchronously or asynchronously

Ring Counter

Shift register in which the output of the last FF is connected back to the input of the first FF.

Johnson Counter

Shift register in which the inverted output of the last FF is connected to the input of the first FF.