Home | | Digital Logic Circuits | Basic Memory Cell of a PROM: Erasable PROM

Chapter: Digital Logic Circuits - Asynchronous Sequential Circuits and Programmable Logic Devices

Basic Memory Cell of a PROM: Erasable PROM

EPROM can be erased and reprogrammed as many times as desired. Once programmed, it is nonvolatile, i.e. it holds the stored data indefinitely.

Basic Memory Cell of a PROM

 

Erasable PROM

 

EPROM can be erased and reprogrammed as many times as desired. Once programmed, it is nonvolatile, i.e. it holds the stored data indefinitely. There are two types of EPROM, namely the ultraviolet-erasable PROM (UV EPROM) and electrically erasable PROM (EEPROM). The memory cell in a UV EPROM is a MOS transistor with a floating gate. In the normal condition,the MOS transistor is OFF. It can be turned ON by applying a programming pulse (in the range 1025 V) that injects electrons into the floating-gate region. These electrons remain trapped in the gate region even after removal of the programming pulse. This keeps the transistor ON once it is programmed to be in that state even after the removal of power. The stored information can, however, be erased by exposing the chip to ultraviolet radiation through a transparent window on the top of the chip meant for the purpose. The photocurrent thus produced removes the stored charge in the floating-gate region and brings the transistor back to the OFF state. The erasing operation takes around 15 20 min, and the process erases information on all cells of the chip. It is not possible to carry out any selective erasure of memory cells. Intel‘s 2732 is 4K× 8 UV EPROM hardware implemented with NMOS devices. Type numbers 2764, 27128, 27256 and 27512 have capacities of 8K× 8, 16K× 8, 32K× 8 and 64K× 8 respectively. The access time is in the range 150250 ns. UV EPROMs suffer from disadvantages such as the need to remove the chip from the circuit if it is to be reprogrammed, the nonfeasibility of carrying out selective erasure and the reprogramming process taking several tens of minutes. These are overcome in the EEPROMs and flash memories discussed in the following paragraphs. The memory cell of an EEPROM is also a floating-gate MOS structure with the slight modification that there is a thin oxide layer above the drain of the MOS memory cell. Application of a high-voltage programming pulse between gate and drain induces charge in the floating-gate region which can be erased by reversing the polarity of the pulse. Since the charge transport mechanism requires very low current, erasing and programming operations can be carried out without removing the chip from the circuit. EEPROMs have another advantage it is possible to erase and rewrite data in the individual bytes in the memory array. The EEPROMs, however, have lower density (bit capacity per square mm of silicon) and higher cost compared with UV EPROMs.


Study Material, Lecturing Notes, Assignment, Reference, Wiki description explanation, brief detail
Digital Logic Circuits - Asynchronous Sequential Circuits and Programmable Logic Devices : Basic Memory Cell of a PROM: Erasable PROM |


Privacy Policy, Terms and Conditions, DMCA Policy and Compliant

Copyright © 2018-2023 BrainKart.com; All Rights Reserved. Developed by Therithal info, Chennai.