MODE, EXCEPTIONS, AND TRAPS:
mechanisms to handle internal conditions, and they are very similar to
interrupts in form. We begin with a discussion of supervisor mode, which some
processors use to handle exceptional events and protect executing programs from
become clearer in later chapters, complex systems are often implemented as
several programs that communicate with each other. These programs may run under
the command of an operating system. It may be desirable to provide hardware
checks to ensure that the programs do not interfere with each other—for
example, by erroneously writing into a segment of memory used by another
program. Software debugging is important but can leave some problems in a
running system; hardware checks ensure an additional level of safety.
cases it is often useful to have a supervisor mode provided by the CPU.
Normal programs run in user mode. The supervisor mode has
privileges that user modes do not. Control of the memory management unit (MMU)
is typically reserved for supervisor mode to avoid the obvious problems that
could occur when program bugs cause inadvertent changes in the memory
CPUs have supervisor modes. Many DSPs, including the C55x, do not provide
supervisor modes. The ARM, however, does have such a mode. The ARM instruction
that puts the CPU in supervisor mode is called SWI:
of course, be executed conditionally, as with any ARM instruction. SWI causes
the CPU to go into supervisor mode and sets the PC to 0x08.The argument to SWI
is a 24-bit immediate value that is passed on to the supervisor mode code; it allows
the program to request various services from the supervisor mode.
supervisor mode, the bottom 5 bits of the CPSR are all set to 1 to indicate
that the CPU is in supervisor mode. The old value of the CPSR just before the
SWI is stored in a register called the saved program status register (SPSR).
There are in fact several SPSRs for different modes; the supervisor mode
SPSR is referred to as SPSR_svc.
from supervisor mode, the supervisor restores the PC from register r14 and
restores the CPSR from the SPSR_svc.
An exception is an internally detected
error. A simple example is division by zero. One way to handle this problem
would be to check every divisor before division to be sure it is not zero, but
this would both substantially increase the size of numerical programs and cost
a great deal of CPU time evaluating the divisor’s value.
The CPU can more efficiently check the divisor’s
value during execution. Since the time at which a zero divisor will be found is
not known in advance, this event is similar to an interrupt except that it is
generated inside the CPU. The exception mechanism provides a way for the
program to react to such unexpected events.
Just as interrupts can be seen as an extension of
the subroutine mechanism, exceptions are generally implemented as a variation
of an interrupt. Since both deal with changes in the flow of control of a
program, it makes sense to use similar mechanisms. However, exceptions are
Exceptions in general require both prioritization
and vectoring. Exceptions must be prioritized because a single operation may
generate more than one exception for example, an illegal operand and an illegal
The priority of exceptions is usually fixed by the
CPU architecture. Vectoring provides a way for the user to specify the handler
for the exception condition.
The vector number for an exception is usually
predefined by the architecture; it is used to index into a table of exception
A trap, also known as a software
interrupt, is an instruction that explicitly generates an exception
condition. The most common use of a trap is to enter supervisor mode.
The entry into supervisor mode must be controlled
to maintain security—if the interface between user and supervisor mode is
improperly designed, a user program may be able to sneak code into the
supervisor mode that could be executed to perform harmful operations.
The ARM provides the SWI interrupt for software
interrupts. This instruction causes the CPU to enter supervisor mode. An opcode
is embedded in the instruction that can be read by the handler.