Recognising an interrupt

Recognising an interrupt

The start of the whole process is the recognition of an interrupt. Internal interrupts are normally defined by the manu-facturer and are already hardwired. External interrupts, however, are not and can use a variety of mechanisms.

Edge triggered

With the edge triggered interrupt, it is the clock edge that is used to generate the interrupt. The transition can either be from a logical high to low or vice versa. With these systems, the recogni-tion process is usually in two stages. The first stage is the external transition that typically latches an interrupt signal. This signal is then checked on an instruction boundary and, if set, starts the interrupt process. At this point, the interrupt has been successfully recognised and the source removed.

Level triggered

With a level triggered interrupt, the trigger is dependent on the logic level. Typically, the interrupt pin is sampled on a regular basis, e.g. after every instruction or on every clock edge. If it is set to the appropriate logic level, the interrupt is recognised and acted upon. Some processors require the level to be held for a minimum number of clocks or for a certain pulse width so that extraneous pulses that are shorter in duration than the minimum pulse width are ignored.

Maintaining the interrupt

So far, the recognition of an interrupt has concentrated on simply asserting the interrupt pin. This implies that provided the minimum conditions have been met, the interrupt source can be removed. Many microprocessor manufacturers recommend that this is not done and that the interrupt should be maintained until it has been explicitly serviced and the source told to remove it.

Internal queuing

This last point also raises a further potential complication. If an interrupt is asserted so that it conforms with the recognition conditions, removed and reasserted, the expectation would be that the interrupt service routine would be executed twice to service each interrupt. This assumes that there is an internal counter within the processor that can count the number of inter-rupts and thus effectively queue them. While this might be ex-pected, this is not the case with most processors. The first interrupt would be recognised and, until it is serviced, all other interrupts generated using the pin are ignored. This is one reason why many processors insist on the maintain until serviced approach with interrupts. Any subsequent interrupts that have the same level will be maintained after the first one has been serviced and its signal removed. When the exception processing is completed, the remaining interrupts will be recognised and processed one by one until they are all serviced.