Instruction restart and continuation

Instruction restart and continuation

The method of continuing the normal execution after ex-ception processing due to a mid-instruction fault, such as that caused by a bus error or a page fault, can be done in one of two ways. Instruction restart effectively backs up the machine to the point in the instruction flow where the error occurred. The proc-essor re-executes the instruction and carries on. The instruction continuation stores all the internal data and allows the errant bus cycle to be restarted, even if it is in the middle of an instruction.

The continuation mechanism is undoubtedly easier for software to handle, yet pays the penalty of having extremely large stack frames or the need to store large amounts of context informa-tion to allow the processor to continue mid-instruction. The restart mechanism is easier from a hardware perspective, yet can pose increased software overheads. The handler has to determine how far back to restart the machine and must ensure that resources are in the correct state before commencing.

The term ‘restart’ is important and has some implications. Unlike many CISC processors (for example, the MC68000, MC68020 and MC68030) the instruction does not continue; it is restarted from the beginning. If the exception occurred in the middle of the instruction, the restart repeats the initial action. For many instruc-tions this may not be a problem — but it can lead to some interesting situations concerning memory and I/O accesses.

If the instruction is accessing multiple memory locations and fails after the second access, the first access will be repeated. The store multiple type of instruction is a good example of this, where the contents of several registers are written out to memory. If the target address is an I/O peripheral, an unexpected repeat access may confuse it.

While the majority of the M68000 and 80x86 families are of the continuation type. The MC68040 and PowerPC families along with most microcontrollers — especially those using RISC architectures — are of the restart type. As processors increase in speed and complexity, the penalty of large stack frames shifts the balance in favour of the restart model.