Interrupt sources

Interrupt sources

There are many sources for interrupts varying from simply asserting an external pin to error conditions within the processor that require immediate attention.

Internal interrupts

Internal interrupts are those that are generated by on-chip peripherals such as serial and parallel ports. With an external peripheral, the device will normally assert an external pin which is connected to an interrupt pin on the processor. With internal peripherals, this connection is already made. Some integrated processors allow some flexibility concerning these hardwired connections and allow the priority level to be adjusted or even masked out or disabled altogether.

External interrupts

External interrupts are the common method of connecting external peripherals to the processor. They are usually provided through external pins that are connected to peripherals and are asserted by the peripheral. For example, a serial port may have a pin that is asserted when there is data present within its buffers. The pin could be connected to the processor interrupt pin so that when the processor sees the data ready signal as an interrupt. The corresponding interrupt service routine would then fetch the data from the peripheral before restoring the previous processing.

Exceptions

Many processor architectures use the term exception as a more generic term for an interrupt. While the basic definition is the same (an event that changes the software flow to process the event) an exception is extended to cover any event, including internal and external interrupts, that causes the processor to change to a service routine. Typically, exception processing is normally coupled with a change in the processor’s mode. This will be described in more detail for some example processors later in this chapter.

The range of exceptions can be large and varied. A MC68000 has a 256 entry vector table which describes about 90 exception conditions with the rest reserved for future expansion. An 8 bit micro may have only a few.

Software interrupts

The advantage of an interrupt is that it includes a mecha-nism to change the program flow and in some processor architectures, to change into a more protected state. This means that an interrupt could be used to provide an interface to other software such as an operating system. This is the function that is provided by the software interrupt. It is typically an instruction or set of instructions that allows a currently executing software sequence to change flow and return using the more normal interrupt mechanism. With devices like the Z80 this function is provided by the SWI (software interrupt instruction). With the MC68000 and PowerPC architectures, the TRAP instruction is used.

To use software interrupts efficiently, additional data to specify the type of request and/or data parameters has to be passed to the specific ISR that will service the software interrupt. This is normally done by using one or more of the processor’s registers. The registers are accessible by the ISR and can be used to pass status information back to the calling software.

It could be argued that there is no need to use software interrupts because branching to different software routines can be achieved by branches and jumps. The advantage that a software interrupt offers is in providing a bridge and routine between software running in the normal user mode and other software running in a supervisor mode. The different modes allow the resources such as memory and associated code and data to be protected from each other. This means that if the user causes a problem or makes an incorrect call, then the supervisor code and data are not at risk and can therefore survive and thus have a chance to restore the system or at least shut it down in an orderly manner.

Non-maskable interrupts

A non-maskable interrupt (NMI) is as its name suggests an external interrupt that cannot be masked out. It is by default at the highest priority of any interrupt and will always be recognised and processed. In terms of a strict definition, it is masked out when the ISR starts to process the interrupt so that it is not repeatedly recognised as a separate interrupt and therefore the non-maskable part refers to the ability to mask the interrupt prior to its assertion.

The NMI is normally used as a last resort to generate an interrupt to try and recover control. This can be presented as either a reset button or connected to a fault detection circuit such as a memory parity or watchdog timer. The 80x86 NMI as used on the IBM PC is probably the most known implementation of this function. If the PC memory subsystem detects a parity error, the parity circuitry asserts the NMI. The associated ISR does very little except stop the processing and flash up a window on the PC saying that a parity error has occurred and please restart the machine.