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Chapter: Microprocessor and Microcontroller - 8086 System Bus Structure

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Interrupts of 80286

The Interrupts of 80286 may be divided into three categories, 1. External or hardware interrupts 2. INT instruction or software interrupts 3. Interrupts generated internally by exceptions

Interrupts of 80286

The Interrupts of 80286 may be divided into three categories,

 

1. External or hardware interrupts

2. INT instruction or software interrupts

3. Interrupts generated internally by exceptions

 

While executing an instruction, the CPU may sometimes be confronted with a special situation because of which further execution is not permitted. While trying to execute a divide by zero instruction, the CPU detects a major error and stops further execution. In this case, we say that an exception has been generated. In other words, an instruction exception is an unusual situation encountered during execution of an instruction that stops further execution. The return address from an exception, in most of the cases, points to the instruction that caused the exception.

 

As in the case of 8086, the interrupt vector table of 80286 requires 1Kbytes of space for storing 256, four-byte pointers to point to the corresponding 256 interrupt service routines (lSR). Each pointer contains a 16-bit offset followed by a 16-bit segment selector to point to a particular ISR. The calculation of vector pointer address in the interrupt vector table from the (8-bit) INT type is exactly similar to 8086.

 

Like 8086, the 80286 supports the software interrupts of type 0 (INT 00) to type FFH (INT FFH).

 

Maskable Interrupt INTR: This is a maskable interrupt input pin of which the INT type is to be provided by an external circuit like an interrupt controller. The other functional details of this interrupt pin are exactly similar to the INTR input of 8086.

 

Non-Maskable Interrupt NMI: It has higher priority than the INTR interrupt.

 

Whenever this interrupt is received, a vector value of 02 is supplied internally to calculate the pointer to the interrupt vector table. Once the CPU responds to a NMI request, it does not serve any other interrupt request (including NMI). Further it does not serve the processor extension (coprocessor) segment overrun interrupt, till either it executes IRET or it is reset. To start with, this clears the IF flag which is set again with the execution of IRET, i.e. return from interrupt.

 

Single Step Interrupt

 

As in 8086, this is an internal interrupt that comes into action, if trap flag (TF) of 80286 is set. The CPU stops the execution after each instruction cycle so that the register contents (including flag register), the program status word and memory, etc. may be examined at the end of each instruction execution. This interrupt is useful for troubleshooting the software. An interrupt vector type 01 is reserved for this interrupt.

 

Interrupt Priorities:

 

If more than one interrupt signals occur simultaneously, they are processed according to their priorities as shown below:


 


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