General Operational Amplifier stages and internal circuit diagrams of IC 741

General Operational Amplifier stages and internal circuit diagrams of IC 741

An operational amplifier generally consists of three stages, namely

1.        A differential amplifier

2.        Additional amplifier stages to provide the required voltage gain and dc level shifting.

3.        An emitter-follower or source follower output stage to provide current gain and low output resistance.

A low-frequency or dc gain of approximately 104 is desired for a general purpose op-amp and hence, the use of active load is preferred in the internal circuitry of op-amp.

The output voltage is required to be at ground, when the differential input voltages are zero, and this necessitates the use of dual polarity supply voltage. Since the output resistance of op-amp is required to be low, a complementary push-pull emitter – follower or source follower output stage is employed. Moreover, as the input bias currents are to be very small of the order of pico amperes, an FET input stage is normally preferred.

Input stage:

The input differential amplifier stage uses p-channel JFETs M₁ and M₂. It employs a three-transistor active load formed by Q₃, Q₄, and Q₅. The bias current for the stage is provided by a two-transistor current source using PNP transistors Q₆ and Q₇. Resistor R₁ increases the o utput resistance seen looking into the collector of Q₄ as indicated by R₀₄. This is necessary to provide bias current stability against the transistor parameter variations. Resistor R₂ establishes a definite bias current through Q₅. A single ended output is taken out at the collector of Q₄.

MOSFET‘s are used in place of JFETs with additional devices in the circuit to prevent any damage for the gate oxide due to electrostatic discharges.

Gain stage:

The second stage or the gain stage uses Darlington transistor pair formed by Q₈ and Q₉ as shown in figure. The transistor Q8 is connected as an emitter follower, providing large input resistance.

Therefore, it minimizes the loading effect on the input differential amplifier stage. The transistor Q₉ provides an additional gain and Q₁₀ acts as an active load for this stage. The current mirror formed by Q₇ and Q₁₀ establishes the bias current for Q₉. The VBE drop across Q₉ and drop across R₅ constitute the voltage drop across R₄, and this voltage sets the current through Q₈. It can be set to a small value, such that the base current of Q₈ also is very less.

Output stage:

The final stage of the op-amp is a class AB complementary push-pull output stage. Q₁₁ is an emitter follower, providing a large input resistance for minimizing the loading effects on the gain stage. Bias current for Q₁₁ is provided by the current mirror formed by Q₇ and Q₁₂, through Q₁₃ and Q₁₄ for minimizing the cross over distortion. Transistors can also be used in place of the two diodes.

The overall voltage gain AV of the op-amp is the product of voltage gain of each stage as given by A_V=|A_d| |A₂||A₃|

Where A_d is the gain of the differential amplifier stage, A₂ is the gain of the second gain stage and A₃ is the gain of the output stage.

IC 741 Bipolar operational amplifier:

The IC 741 produced since 1966 by several manufactures is a widely used general purpose operational amplifier. Figure shows that equivalent circuit of the 741 op-amp, divided into various individual stages. The op-amp circuit consists of three stages.

1.     The input differential amplifier

2.     The gain stage

3.     the output stage.

A bias circuit is used to establish the bias current for whole of the circuit in the I_C. The op-amp is supplied with positive and negative supply voltages of value ± 15V and the supply voltages as low as ±5V can also be used.

Bias Circuit:

The reference bias current IREF for the 741 circuit is established by the bias circuit consisting of two diodes-connected transistors Q₁₁ and Q₁₂ and resistor R₅. The Widlar current source formed by Q₁₁, Q₁₀ and R₄ provide bias current for the differential amplifier stage at the collector of Q₁₀. Transistors Q₈ and Q₉ form another current mirror providing bias current for the differential amplifier. The reference bias current IREF also provides mirrored and proportional current at the collector of the double –collector lateral PNP transistor Q₁₃. The transistor Q₁₃ and Q₁₂ thus form a two-output current mirror with Q₁₃A providing bias current for output stage and Q13B providing bias current for Q₁₇. The transistor Q₁₈ and Q₁₉ provide dc bias for the output stage. Formed by Q₁₄ and Q₂₀ and they establish two VBE drops of potential difference between the bases of Q₁₄ and Q₁₈.

Input stage:

The input differential amplifier stage consists of transistors Q1 through Q7 with biasing provided by Q8 through Q12. The transistor Q1 and Q2 form emitter – followers contributing to high differential input resistance, and whose output currents are inputs to the common base amplifier using Q3 and Q4 which offers a large voltage gain. The transistors Q5, Q6 and Q7 along with resistors R1, R2 and R3 from the active load for input stage. The single-ended output is available at the collector of Q6. The two null terminals in the input stage facilitate the null adjustment. The lateral PNP transistors Q3 and Q4 provide additional protection against voltage breakdown conditions. The emitter-base junction Q3 and Q4 have higher emitter-base breakdown voltages of about 50V. Therefore, placing PNP transistors in series with NPN transistors provide protection against accidental shorting of supply to the input terminals.

Gain Stage:

The Second or the gain stage consists of transistors Q₁₆ and Q₁₇, with Q₁₆ acting as an emitter – follower for achieving high input resistance. The transistor Q₁₇ operates in common emitter configuration with its collector voltage applied as input to the output stage. Level shifting is done for this signal at this stage.

Internal compensation through Miller compensation technique is achieved using the feedback capacitor C1 connected between the output and input terminals of the gain stage.

Output stage:

The output stage is a class AB circuit consisting of complementary emitter follower transistor pair Q₁₄ and Q₂₀. Hence, they provide an effective loss output resistance and current gain. The output of the gain stage is connected at the base of Q₂₂, which is connected as an emitter follower providing a very high input resistance, and it offers no appreciable loading effect on the gain stage. It is biased by transistor Q₁₃A which also drives Q18 and Q19, that are used for establishing a quiescent bias current in the output transistors Q₁₄ and Q₂₀.