FET Biasing

FET Biasing

The Parameters of FET is temperature dependent .When temperature increases drain resistance also increases, thus reducing the drain current.

Unlike BJTs, thermal runaway does not occur with FETs

However, the wide differences in maximum and minimum transfer characteristics make I_D levels unpredictable with simple fixed-gate bias voltage.

Different biasing circuits of FET are

1.     Fixed bias circuits

2.     Self bias circuits

3.     Voltage bias circuits

Fixed bias circuits

DC bias of a FET device needs setting of gate-source voltage V_GS to give desired drain current I_D . For a JFET drain current is limited by the saturation current I_DS. Since the FET has such a high input impedance that no gate current flows and the dc voltage of the gate set by a voltage divider or a fixed battery voltage is not affected or loaded by the FET.

Fixed dc bias is obtained using a battery V_QG. This battery ensures that the gate is always negative with respect to source and no current flows through resistor R_G and gate terminal that is I_G =0. The battery provides a voltage V_GS to bias the N-channel JFET, but no resulting current is drawn from the battery V_GG. Resistor R_G is included to allow any ac signal applied through capacitor C to develop across R_G. While any ac signal will develop across R_G, the dc voltage drop across R_G is equal to I_G R_Gi.e. 0 volt.

Calculate V_GS

For DC analysis I_G =0., applying KVL to the input circuits

V_GS+ V_GG=0

V_GS= - V_GG

As V_GS is a fixed dc supply, hence the name fixed bias circuit

Calculate I_DQ

I_DQ=IDss(1- V_GS/V_Gp)²

Calculate V_DS

This current I_DQ then causes a voltage drop across the drain resistor R_D and is given as

V_DSQ = V_DD – I_D R_D

Disadvantage

The fixed bias circuit of FET requires two power supplies.

Self-Bias circuits

Self-Bias circuits is the most common method for biasing a JFET. Self-bias circuit for N-channel JFET is shown in figure

The gate source junction of JFET must be always in reverse biased condition .No gate current flows through the reverse-biased gate-source, the gate current I_G = 0 and, therefore,v_G = i_G R_G = 0

With a drain current I_D the            voltage at the S is

V_s= I_DR_s

1)The gate-source voltage is then

V_GS = V_G - V_s = 0 – I_D R_S = – I_D R_S

So voltage drop across resistance R_s provides the biasing voltage V_Gg and no external source is required for biasing and this is the reason that it is called self-biasing. 2)Calculate I_DQ

I_D=I_DSS(1- V_GS/ V_P)²

Substituting the value of VGS

I_D= I_DSS (1+I_DR_{S  /} V_P)²

3)The operating point (that is zero signal I_D and V_DS) can easily be determined from equation given below :

V_DS = V_DD – I_D(R_D + R_S)

Self biasing of a JFET stabilizes its quiescent operating point against any change in its parameters like transconductance. Any increase in voltage drop across R_S, therefore, gate-source voltage, V_GS becomes more negative and thus increase in drain current is reduced.

Voltage -Divider Bias circuits

The resistors R_Gl and R_G2 form a potential divider across drain supply V_DD. The voltage V₂ across R_G2 provides the necessary bias. The additional gate resistor R_Gl from gate to supply voltage facilitates in larger adjustment of the dc bias point and permits use of larger valued R_S.

The coupling capacitors are assumed to be open circuit for DC analysis

1) The gate is reverse biased so that I_G = 0 and gate voltage

V_G =V₂ = (V_DD/R _{G1 +} R _G2 ) *R_G2

2) Applying KVL to the input circuit we get

V_GS= V_G – V_S = V_G - I_D R_S

3) I_DQ= I_DSS(1- V_GS/ V_P)²

4) V_DS = V_DD – I_D (R_D + R_S)

The operating point of a JFET amplifier using the Voltage -Divider Bias is determined by

I_DQ= I_DSS(1- V_GS/ V_P)²

V_DSQ = V_DD – I_D (R_D + R_S)

V_GSQ = V_G – I_D R_S

Example Problems

1)Determine I_DQ, V_GSQ, V_D, V_S, V_DS, and V_DG