The Parameters of FET is temperature dependent .When temperature increases drain resistance also increases, thus reducing the drain current.

**FET Biasing**

The
Parameters of FET is temperature dependent .When temperature increases drain
resistance also increases, thus reducing the drain current.

Unlike
BJTs, thermal runaway does not occur with FETs

However,
the wide differences in maximum and minimum transfer characteristics make I_{D}
levels unpredictable with simple fixed-gate bias voltage.

Different
biasing circuits of FET are

1.
Fixed bias circuits

2.
Self bias circuits

3.
Voltage bias circuits

**Fixed bias circuits**

DC bias
of a FET device needs setting of gate-source voltage V_{GS} to give
desired drain current I_{D} . For a JFET drain current is limited by
the saturation current I_{DS}. Since the FET has such a high input
impedance that no gate current flows and the dc voltage of the gate set by a
voltage divider or a fixed battery voltage is not affected or loaded by the
FET.

Fixed dc
bias is obtained using a battery V_{QG}. This battery ensures that the
gate is always negative with respect to source and no current flows through
resistor R_{G} and gate terminal that is I_{G} =0. The battery
provides a voltage V_{GS} to bias the N-channel JFET, but no resulting
current is drawn from the battery V_{GG}. Resistor R_{G} is
included to allow any ac signal applied through capacitor C to develop across R_{G}.
While any ac signal will develop across R_{G}, the dc voltage drop
across R_{G} is equal to I_{G} R_{G}*i.e.* 0 volt.

**Calculate V _{GS}**

For DC
analysis I_{G} =0., applying KVL to the input circuits

V_{GS}+
V_{GG}=0

V_{GS}=
- V_{GG}

As V_{GS}
is a fixed dc supply, hence the name fixed bias circuit

**Calculate I _{DQ}**

I_{DQ}=IDss(1-
V_{GS}/V_{Gp})^{2}

**Calculate V _{DS}**

This
current I_{DQ} then causes a voltage drop across the drain resistor R_{D}
and is given as

V_{DSQ}
= V_{DD} – I_{D} R_{D}

**Disadvantage**

The fixed
bias circuit of FET requires two power supplies.

**Self-Bias circuits**

Self-Bias
circuits is the most common method for biasing a JFET. Self-bias circuit for
N-channel JFET is shown in figure

The gate
source junction of JFET must be always in reverse biased condition .No gate
current flows through the reverse-biased gate-source, the gate current I_{G}
= 0 and, therefore,v_{G} = i_{G} R_{G} = 0

With a drain
current I_{D} the voltage
at the S is

V_{s}=
I_{D}R_{s}

1)The
gate-source voltage is then

V_{GS}
= V_{G} - V_{s} = 0 – I_{D} R_{S} = – I_{D}
R_{S}

So
voltage drop across resistance R_{s} provides the biasing voltage V_{Gg}
and no external source is required for biasing and this is the reason that it
is called self-biasing. 2)Calculate I_{DQ}

I_{D=}I_{DSS}(1-
V_{GS/} V_{P})^{2}

Substituting
the value of VGS

I_{D=}
I_{DSS} (1+I_{D}R_{S
/} V_{P})^{2}

3)The
operating point *(*that is zero signal
I_{D} and V_{DS}) can easily be determined from equation given
below :

V_{DS}
= V_{DD} – I_{D}**(**R_{D}
+ R_{S})

Self
biasing of a JFET stabilizes its quiescent operating point against any change
in its parameters like transconductance. Any increase in voltage drop across R_{S},
therefore, gate-source voltage, V_{GS} becomes more negative and thus
increase in drain current is reduced.

**Voltage -Divider Bias circuits**

The
resistors R_{Gl} and R_{G2} form a potential divider across
drain supply V_{DD}. The voltage V_{2} across R_{G2}
provides the necessary bias. The additional gate resistor R_{Gl} from
gate to supply voltage facilitates in larger adjustment of the dc bias point
and permits use of larger valued R_{S}.

The
coupling capacitors are assumed to be open circuit for DC analysis

1) The
gate is reverse biased so that I_{G} = 0 and gate voltage

V_{G}
=V_{2} = (V_{DD}/R _{G1 +} R _{G2} ) *R_{G2}

2) Applying
KVL to the input circuit we get

V_{GS}**= V**_{G} – V_{S} = V_{G}
- I_{D} R_{S}

3) I_{DQ}=
I_{DSS}(1- V_{GS}/ V_{P})^{2}

4) V_{DS}
= V_{DD} – I_{D} (R_{D} + R_{S})

The
operating point of a JFET amplifier using the Voltage -Divider Bias is
determined by

I_{DQ}=
I_{DSS}(1- V_{GS}/ V_{P})^{2}

V_{DSQ}
= V_{DD} – I_{D} (R_{D} + R_{S})

V_{GSQ}
= V_{G} – I_{D} R_{S}

**Example Problems**

1)Determine
I_{DQ,} V_{GSQ,} V_{D,} V_{S,} V_{DS,}
and V_{DG}

Study Material, Lecturing Notes, Assignment, Reference, Wiki description explanation, brief detail

Electronic Circuits : Biasing of Discrete BJT and MOSFET : FET Biasing |

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