APPLICATION SPECIFIC –ICs
Perhaps the most interesting
developments in IC technology for the average digital designer are not the
ever-increasing chip sizes, but the ever-increasing opportunities
to “design your own chip.” Chips designed for a particular,
limited product or applications are called semicustom ICs or
application-specific ICs (ASICs). ASICs generally reduce the total
component and manufacturing cost of a product by reducing chip count, physical
size, and power consumption, and they often provide higher performance.
The nonrecurring engineering
(NRE) cost for designing an ASIC can exceed the cost of a discrete design
by $5,000 to $250,000 or more.
The NRE cost to design a custom
LSI chip— a chip whose functions, internal
architecture, and detailed transistor-level design is tailored for a specific
customer— is very high, $250,000 or more.
Thus, full custom LSI design is done only for chips that have general
commercial application or that will enjoy very
high sales volume in a specific
application (e.g., a digital watch chip, a network interface, or a
bus-interface circuit for a PC).
To reduce NRE charges, IC
manufacturers have developed libraries of standard cells
including commonly used MSI functions such as decoders, registers, and
counters, and commonly used LSI functions such as memories, programmable logic
arrays, and microprocessors.
In a standard-cell design,
the logic designer interconnects functions in much the same way as in a
multichip MSI/LSI design. Custom cells are created only if absolutely
necessary. All of the cells are then laid out on the chip, optimizing the
layout to reduce propagation delays and minimize the size of the chip.
A gate array is an IC whose internal structure
is an array of gates whose interconnections are initially
logic designer specifies
the gate types and
interconnections. Even though
design is ultimately specified at
this very low level, the designer typically works with
“macrocells, same high-level functions used in multichip
MSI/LSI and standard-cell designs; software expands the high-level design into
a low-level one.
The main difference between
standard-cell and gate-array design is that the macrocells and the chip layout
of a gate array are not as highly optimized as those in a standard-cell design,
so the chip may be 25% or more larger, and therefore may cost more.