Binary-Weighted
Resistor DAC
The
binary-weighted-resistor DAC employs the characteristics of the inverting
summer Op Amp circuit. In this type of DAC, the output voltage is the inverted
sum of all the input voltages. If the input resistor values are set to
multiples of two: 1R, 2R and 4R, the output voltage would be equal to the sum
of V1, V2/2 and V3/4.
V1 corresponds to the most
significant bit (MSB) while V3 corresponds to the least significant
bit (LSB).
The
circuit for a 4-bit DAC using binary weighted resistor network is shown below:
The
binary inputs, ai (where i = 1, 2, 3 and 4) have values of either 0 or 1. The
value, 0, represents an open switch while 1 represents a closed switch.
The
operational amplifier is used as a summing amplifier, which gives a weighted
sum of the binary input based on the voltage, Vref.
For
a 4-bit DAC, the relationship between Vout and the binary input is as follows:
The
negative sign associated with the analog output is due to the connection to a
summing amplifier, which is a polarity-inverting amplifier. When a signal is applied
to the latter type of amplifier, the polarity of the signal is reversed (i.e. a
+ input becomes -, or vice versa).
For
a n-bit DAC, the relationship between Vout and the binary input is as follows:
The
LSB, which is also the incremental step, has a value of - 0.625 V while the MSB
or the full scale has a value of - 9.375 V.
o The most significant problem is the large
difference in resistor values required between the LSB and MSB, especially in
the case of high resolution DACs (i.e. those that has large number of bits).
For example, in the case of a 12-bit DAC, if the MSB is 1 k Ω, then the LSB is
a staggering 2 MΩ.
o The maintenance of accurate resistances over
a large range of values is problematic. With the current IC fabrication
technology, it is difficult to manufacture resistors over a wide resistance
range that maintains an accurate ratio especially with variations in
temperature.
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