Emitter-coupled logic (ECL) is a non saturated digital logic family. Since transistors do not saturate. it is possible to achieve propagation delays as low as 1-2 ns. This logic family has the lowest propagation delay of any family and is used mostly in systems requiring very high speed operation. Its noise immunity and power dissipation . however. are the worst of all the logic families available. A typical basic circuit of the ECL family is shown in Fig The outputs provide both the OR and NOR function s. Each input is connected to the base of a transistor. The two voltage levels are about - 0.8 V for the high state and about - 1.8 V for the low state. The circuit consists of a differential amplifier. a temperature- and voltage-compensated bias network. And an emitter-follower output. The emitter outputs require a pull-down resistor for current to flow. This is obtained from the input resistor Rp of another similar gate or from an ex tern al resistor connected to a negative voltage supply.
The internal temperature- and voltage-compensated bias circuit supplies a reference volt age to the differential amplifier. Bias voltage Vss is set at - 1.3 V, which is me midpoint of me signal's logic swing. The diodes in the voltage divider to get ber with Q6. provide a circuit that maintain s a constant VBs value despite changes in temperature or supply voltage. Any one of the power supply inputs could be used as ground. However, the use of the Vcc node as ground and VEE at - 5.2 V results in the best noise immunity.
If any input in the ECL gat e is high. the corresponding transistor is tunned OIl and Q5 is turned off .An input of - 0.8 V causes the transistor lO conduct and places -1.6 V OIl the emitters of all of the transistors. (The VB£ drop in EeL transistors is 0.8 V.) Since VBB = - 1.3 V, the base voltage of Q5 is only 0.3 V more positive man its emitter. Q5 is cut off because its VBE voltage needs at least 0.6 V to start conducting. The current in resistor Rc: flows into the base of Q8 (provided that there is a load resistor). This current is so small that only a negligible voltage drop occurs across Rcz-The OR output of the gate is one VBE drop below ground. Or - 0.8 V. which is the high stale. The current flowing through RCI and the conducting transistor causes a drop of about 1 V below ground.The l'\OR output is one VBE drop below this level. or - 1.8 V. which is the low state.
If all inputs are at the low leve l, all input transistors turn off and Q5 conduct s. The voltage in the common-emitter node is one VBE drop below VBB, or - 2.1 V. Since the base of each input is at a low level of - 1.8 V. each base-emitter junction has only 0.3 V and all input transistors are cut off. RCl draws current thro ugh Q5 that results in a voltage drop of about I V, making the OR output one VBE drop below this. at -1.8 V. or the low leve l. The current in RCl is negligible and the nor output is one VBE drop below ground, at - 0.8 V. or the high level. This analysis verifies the OR and NOR operations of the circuit.
The propagation delay of the Ee L gale is 2 ns and the power dissipation is 25 mw, giving a speed-power product of 50. which is about the same as that for the Schottky TIL. The noise margin is about 0.3 V and is not as good as that in the TTL gate. High fan-out is possible in the ECl gate because of the high input impedance of the differential amplifier and the low output impedance of the emitter-follower. Because of the extreme high speed of the signals. external wires act like transmission lines. Except for very sha lt wires of a few centimeters .ECl outputs must use coaxial cables with a resistor termination to redu ce line reflection s.The grphic symbol for the ECl gate shown in Fig. 10.18(a). 'Two outputs are available: one for the NOR function and the other for the OR function. The outputs of two or more ECL gate s can be connected together to form wired logic. As shown in Fig. 1O.18(b), an external wired connection of two NOR outputs produces a wired-OR function. An internal wired connection of two OR outputs is employed in some Eel ICs to produce a wired-AND (sometimes called dot-AND) logic. This property may be utilized when ECL gales are used to form the OR- AND- INVE RT and the OR-AND functions.