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BIT BINARY PARALLEL ADDER AND SUBTRACTOR:
To add two 4-bit binary number, we proceed as shown in the table. The table shows the role of carry-in and carry-out.
4-bit binary parallel adder can be implemented in integrated circuit form by cascading 4 full adders as shown below. The disadvantage of this adder is the possible slowing down of the addition due to the carry propagation time.
The 4-bit parallel adder can be modified to work as 4-bit parallel adder/subtractor b including 4 exclusive-OR gates to provide the 1's complement of B and adding 1 from the M input to make it the 2's complement.
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