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Chapter: Distributed Systems - Process & Resource Management

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Other Consistency Models

Models of memory consistency can be divided into uniform models, which do not distinguish between types of memory access, and hybrid models, which do distinguish between ordinary and synchronization accesses (as well as other types of access).

OTHER CONSISTENCY MODELS

 

Models of memory consistency can be divided into uniform models, which do not distinguish between types of memory access, and hybrid models, which do distinguish between ordinary and synchronization accesses (as well as other types of access).

 

Other uniform consistency models include:

 

Causal consistency: Reads and writes may be related by the happened-before relationship . This is defined to hold between memory operations when either (a) they are made by the same process; (b) a process reads a value written by another process; or (c) there exists a sequence of such operations linking the two operations. The model’s constraint is that the value returned by a read must be consistent with the happened-before relationship.

 

Processor consistency: The memory is both coherent and adheres to the pipelined RAM model (see below). The simplest way to think of processor consistency is that the memory is coherent and that all processes agree on the ordering of any two write accesses made by the same process

 

that is, they agree with its program order.

 

Pipelined RAM: All processors agree on the order of writes issued by any given processor In addition to release consistency, hybrid models include:

 

Entry consistency: Entry consistency was proposed for the Midway DSM system. In this model, every shared variable is bound to a synchronization object such as a lock, which governs access to that variable. Any process that first acquires the lock is guaranteed to read the latest value of the variable. A process wishing to write the variable must first obtain the corresponding lock in

 

‘exclusive’ mode – making it the only process able to access the variable.

 

Several processes may read the variable concurrently by holding the lock in nonexclusive mode. Midway avoids the tendency to false sharing in release consistency, but at the expense of increased programming complexity.

 

Scope consistency: This memory model [Iftode et al. 1996] attempts to simplify the programming model of entry consistency. In scope consistency, variables are associated with synchronization objects largely automatically instead of relying on the programmer to associate locks with variables explicitly. For example, the system can monitor which variables are updated in a critical section.

 

Weak consistency: Weak consistency [Dubois et al. 1988] does not distinguish between acquire and release synchronization accesses. One of its guarantees is that all previous ordinary accesses complete before either type of synchronization access completes.


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