EPIC (Explicitly Parallel Instruction Computing)

EPIC (Explicitly Parallel Instruction Computing)

EPIC permits microprocessors to execute software instructions in parallel by using the compiler, rather than complex on-die circuitry, to control parallel instruction execution.This was intended to allow simple performance scaling without resorting to higher clock frequencies.

It was the basis for Intel and HP development of the Intel Itanium architecture Intel/HP

EPIC/IA-64 Architecure. EPIC is ISA philosophy approach. Very closely related to but not the same as VLIW.IA-64 an ISA definition. Intel’s new 64-bit ISA. An EPIC type ISA

Itanium

A processor implementation of an ISA. The first implementation of the IA-64 ISA EPIC. EPIC design style Specifies ILP explicit in the machine code, that is, the parallelism is encoded directly into the instructions similarly to VLIW. A fully predicated instruction set. An inherent scalable instruction set. Many register Speculative execution of load instructions. EPIC instruction word contains three 41-bit instructions and a 5-bit control field.

EPIC design challenges

Develop architectures applicable to general-purpose computing. Find substantial parallelism in “difficult to parallellize” scalar programs. Provide compatibility across hardware generations. Support emerging applications. Compiler must find or create sufficient ILP. •

Combine the best attributes of VLIW & superscalar RISC.Scale architectures for modern single-chip implementation

IA-64 EPIC Architecture

Instruction set architecture has128 64-bit integer registers + 128 82-bit floating points. Not separate register files per functional unit as in VLIW. Hardware checks dependencies (interlocks => binary compatibility over time).Predicated execution (select 1 out of 64 1-bit flags)

Instruction group is a sequence of consecutive instructions with no register data dependencies. All the instructions in a group could be executed in parallel, if sufficient hardware resources existed and if any dependence through memory were preserved

An instruction group can be arbitrarily long, but the compiler must explicitly indicate the boundary between one instruction group and another by placing a stop between 2 instructions that belong to different groups.IA-64 EPIC instructions are encoded in bundles, which are 128 bits wide

 IA-64 EPIC vs VLIW

Similarities

Ø Compiler generated wide instructions

Ø Static detection of dependencies

Ø ILP encoded in the binary

Ø Large number of architected registers

Differences

Ø Instructions in a bundle can have dependencies

Ø Hardware interlock between dependent instructions

Ø Accommodates varying number of functional units and latencies

Ø Allows dynamic scheduling and functional unit binding

Ø Code size is reduced

Ø The same code can be executed on different processor implementations (ex: different number of functional units)

Ø Compiler detects ILP and indicates when an instruction cannot be executed in parallel with its

Ø successors