Chapter: Computer Architecture - Processor and Control Unit

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Pipelining

Pipelining is an implementation technique whereby multiple instructions are overlapped in execution

PIPELINING

Basic concepts

 

·     Pipelining is an implementation technique whereby multiple instructions are overlapped in execution

 

·     Takes advantage of parallelism

·     Key implementation technique used to make fast CPUs.

·     A pipeline is like an assembly line.

 

In a computer pipeline, each step in the pipeline completes a part of an instruction.Like the assembly line, different steps are completing different parts of different instructions in parallel. Each of these steps is called a pipe stage or a pipe segment.

 

·     The stages are connected one to the next to form a pipe—instructions enter at one end, progress through the stages, and exit at the other end.

 

·     The throughput of an instruction pipeline is determined by how often an instruction exits the pipeline.

 

·     The time required between moving an instruction one step down the pipeline is a processor cycle..

 

·     If the starting point is a processor that takes 1 (long) clock cycle per instruction, then pipelining decreases the clock cycle time.

 

·     Pipeline for an integer subset of a RISC architecture that consists of load-store word, branch, and integer ALU operations.

 

Every instruction in this RISC subset can be implemented in at most 5 clock cycles. The 5 clock cycles are as follows.

 

1. Instruction fetch cycle (IF):

 

Send the program counter (PC) to memory and fetch the current instruction from memory. PC=PC+4

 

2. Instruction decode/register fetch cycle (ID):

 

Ø     Decode the instruction and read the registers.

Ø     Do the equality test on the registers as they are read, for a possible branch.

 

Ø     Compute the possible branch target address by adding the sign-extended offset to the incremented PC.

 

Ø     Decoding is done in parallel with reading registers, which is possible because the register specifiers are at a fixed location in a RISC architecture,known as fixed-field decoding

 

3. Execution/effective address cycle(EX):

 

The ALU operates on the operands prepared in the prior cycle, performing one of three functions depending on the instruction type.

 

Ø     Memory reference: The ALU adds the base register and the offset to form the effective address.

 

Ø     Register-Register ALU instruction: The ALU performs the operation specified by the ALU opcode on the values read from the register file

Ø     Register-Immediate ALU instruction: The ALU performs the operation specified by the ALU opcode on the first value read from the register file and the sign-extended immediate.

 

4. Memory access(MEM):

 

Ø     If the instruction is a load, memory does a read using the effective address computed in the previous cycle.

 

Ø     If it is a store, then the memory writes the data from the second register read from the register file using the effective address.

 

5. Write-back cycle (WB):

Register-Register ALU instruction or Load instruction: Write the result into the register file, whether it comes from the memory system (for a load) or from the ALU (for an ALU instruction).


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