PIPELINED
DATA PATH AND CONTROL
The Classic Five-Stage
Pipeline for a RISC Processor
Each of the clock
cycles from the previous section becomes a pipe stage—a cycle in the pipeline.
Each instruction takes
5 clock cycles to complete, during each clock cycle the hardware will initiate
a new instruction and will be executing some part of the five different
instructions.
3 observations:
1. Use
separate instruction and data memories, which implement with separate
instruction and data caches.
2. The
register file is used in the two stages: one for reading in ID and one for
writing in WB, need to perform 2 reads and one write every clock cycle.
3. Does
not deal with PC, To start a new instruction every clock, we must increment and
store the PC every clock, and this must be done during the IF stage in
preparation for the next instruction.
To ensure that
instructions in different stages of the pipeline do not interfere with one
another. This separation is done by introducing pipeline registers between
successive stages of the pipeline, so that at the end of a clock cycle all the
results from a given stage are stored into a register that is used as the input
to the next stage on the next clock cycle.
Related Topics
Privacy Policy, Terms and Conditions, DMCA Policy and Compliant
Copyright © 2018-2024 BrainKart.com; All Rights Reserved. Developed by Therithal info, Chennai.