Chapter: Digital Principles and System Design : Combinational logic
Hardware Description Language(HDL)
Hardware Description Language(HDL)
INTRODUCTION TO HDL
In electronics, a hardware description language or HDL
is any language from a class of computer languages and/or programming languages
for formal description of digital logic and electronic circuits. HDLs are used
to write executable specifications of some piece of hardware. A simulation
program, designed to implement the underlying semantics of the language
statements, coupled with simulating the progress of time, provides the hardware
designer with the ability to model a piece of hardware before it is created
physically.
HDL MODELS OF
COMBINATIONAL CIRCUITS.
The Verilog HDL model of a combinational circuit can be
described in any one of the following modeling styles,
ü Gate
level modeling-using instantiations of predefined and user defined primitive
gates.
ü Dataflow
modeling using continuous assignment with the keyword assign.
ü Behavioral
modeling using procedural assignment statements with the keyword always.
Ø Gate
level modeling
In this type, a circuit is specified by its logic
gates and their interconnections. Gate level modeling provides a textual
description of a schematic diagram. The verilog HDL includes 12 basic gates as
predefined primitives. They are and, nand, or, nor, xor, xnor, not & buf.
ØDataflow
Dataflow modeling of combinational logic uses a
number of operators that act on operands to produce desired results. Verilog
HDL provides about 30 different operators. Dataflow modeling uses continuous
assignments and the keyword assign. A continuous assignment is a
statement that assigns a value to a net. The data type family net is
used to represent a physical connection between circuit elements.
Ø Behavioral modeling
Behavioral modeling represents digital circuits at
a functional and algorithmic level. It is used mostly to describe sequential
circuits, but can also be used to describe combinational circuits. Behavioral
descriptions use the keyword always, followed by an optional event
control expression and a list of procedural assignment statements.
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