Chapter: Engineering College Final Year project Titles , EEE ECE EI Mech Dept Department Idea Report download

LIST OF IEEE VLSI PROJECTS 2018-2019

Engineering College Final Year project , Electrical and Electronics Department,Electronics and communication Department, Embedded Department , Mechanical Department (EEE Dept , ECE Dept., E&I Dept )

A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories
A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering
A Computationally Efficient Delay less Frequency-Domain Adaptive Filter Algorithm
A Linear Programming Based Tone Injection Algorithm for PAPR Reduction of OFDM and Linearly Precoded Systems
A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks
A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits
Aliasing-Free Digital Pulse-Width Modulation for Burst-Mode RF Transmitters
Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits
Glitch-Free NAND-Based Digitally Controlled Delay-Lines
IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter with Low Adaptation-Delay
Broadside and Skewed-Load Tests under Primary Input Constraints
Built-In Generation of Functional Broadside Tests using a Fixed Hardware Structure
Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip
Design of Hardware Function Evaluators using Low-Overhead Nonuniform Segmentation with Address Remapping
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops
Efficiency Optimization for Burst-Mode Multilevel Radio Frequency Transmitters
Efficient Implementation of Reconfigurable Warped Digital Filters With Variable Low-Pass, High-Pass, Band pass, and Band stop Responses
Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture
Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function
Eliminating Synchronization Latency Using Sequenced Latching
Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes
Low-Power Area-Efficient High-Speed I/O Circuit Techniques
Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes
Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic
Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements
MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems
Multivoltage Aware Resistive Open Fault Model
Oscillation and Transition Tests for Synchronous Sequential Circuits
Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment
RATS: Restoration-Aware Trace Signal Selection for Post-Silicon Validation
Reduced-Complexity LCC Reed-Solomon Decoder Based on Unified Syndrome Computation
Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories
Smart Reliable Network-on-Chip
Split-SAR ADCs: Improved Linearity With Power and Speed Optimization
Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD
Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches
The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures
Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed
Time-Based All-Digital Technique for Analog Built-in Self-Test
Two-Tone Phase Delay Control of Center Frequency and Bandwidth in Low-Noise-Amplifier RF Front Ends
Unique Measurement and Modeling of Total Phase Noise in RF Receiver
VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture
WLS Design of Sparse FIR Digital Filters
A 10-T SRAM cell with Inbuilt Charge Sharing for Dynamic Power Reduction
A Current-Starved Inverter-based Differential Amplifier Design for Ultra-Low Power Applications
A Fast Low-Light Multi-Image Fusion with Online Image Restoration
A High Performance D-Flip Flop Design with Low Power Clocking System using MTCMOS
A Low Power Fault Tolerant Reversible Decoder using MOS Transistor
A Low Power Single Phase Clock Distribution using VLSI technology
A Novel modulo Adder for 2n-2k-1 Residue Number System
A Novel Transistor Level Realization of Ultra Low Power High-Speed Adiabatic Vedic Multiplier
A Topology-Based Model for Railway Train Control Systems
Achieving Reduced Area by Multi-Bit Flip Flop Design
An Analysis of SOBEL and GABOR Image Filters for Identifying Fish
An Efficient Denoising Architecture for Removal of Impulse Noise in Images
An Efficient High Speed Wallace Tree Multiplier
An Efficient SQRT Architecture of Carry Select Adder Design by Common Boolean Logic
An Interactive RFID-based Bracelet for Airport Luggage Tracking System
Area-Delay Efficient Binary Adders in QCA
Asynchronous Design of Energy Efficient Full Adder
Background Subtraction Based on Threshold detection using Modified K-Means Algorithm
Comparison of Static and Dynamic Printed Organic Shift Registers
CORDIC based Fast Radix-2 DCT Algorithm
Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
Design of Digit-Serial FIR Filters: Algorithms, Architectures and a CAD Tool
Design of High Speed Low Power Viterbi Decoder for TCM System
Design of Low Energy, High Performance Synchronous and Asynchronous 64-Point FFT
Design of Low Power Sequential Circuit Using Clocked Pair Shared Flip flop
FFT Architectures for Real-Valued Signals Based on Radix-2by3 & Radix-2by4 Algorithms
Fixed-Width Multipliers and Multipliers- Accumulators with Min-Max Approximation Error
FPGA Implementation of Pipelined Architecture For SPIHT Algorithm
Hardware Implementation of a Digital Watermarking System for Video Authentication
High-Throughput Compact Delay-Insensitive Asynchronous NOC Router
High-Throughput Multi standard Transform Core Supporting MPEG/H.264/VC-1 using Common Sharing Distributed Arithmetic
Improvement of the Security of Zigbee by a New Chaotic Algorithm
Least Significant Bit Matching Steganalysis based on Feature Analysis
Location-Aware and Safer Cards: Enhancing RFID Security and Privacy via Location Sensing
Low Latency Systolic Montgomery Multiplier for Finite Field Based on Pentanomials
Low-Complexity Multiplier for GF (2m) based on All-One Polynomials
Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Soft-core Processor
Low-Power Digital Signal Processing Using Approximate Adders
Memory efficient high-Speed convolution-based generic structure for multilevel 2D DWT
Modified Gradient Search for Level Set Based Image Segmentation
Multicarrier Systems based on Multistage Layered IFFT Structure
Optical Flow Estimation for Flame Detection in Videos
Parallel AES Encryption Engines for Many-Core Processor Arrays
Performance Analysis of a New CMOS Output Buffer
Performance Evaluation of FFT Processor Using Conventional and Vedic Algorithm
Pipelined Radix-2k Feed forward FFT Architectures
Prototype of a Fingerprint Based Licensing System For Driving
Real Time Communication between Multiple FPGA Systems in Multitasking Environment Using RTOS
Reconfigurable Processor for Binary Image Processing
Reduction of Leakage Current and Power in Full Subtractor Using MTCMOS Technique
Reverse Circle Cipher for Personal and Network Security
RFID-based Location System for Forest Search and Rescue Missions
RFID-based Tracking System Preventing Trees Extinction and Deforestation
Satellite Image Enhancement Using Discrete Wavelet Transform and Threshold Decomposition Driven Morphological Filter
Secure Transmission in Downlink Cellular Network with a Cooperative Jammer
Segmentation and Location of Abnormality in Brain MR Images using Distributed Estimation
Selective Eigen background for Background Modeling & Subtraction in Crowded Scenes
Shadow Removal for Background Subtraction Using Illumination Invariant Measures
Teaching HW/SW Co-Design with a Public Key Cryptography Application
Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes
The Security Technology and Tendency of New Energy Vehicle in Future

Study Material, Lecturing Notes, Assignment, Reference, Wiki description explanation, brief detail

Engineering College Final Year project Titles , EEE ECE EI Mech Dept Department Idea Report download : LIST OF IEEE VLSI PROJECTS 2018-2019 |