Chapter: Engineering College Final Year project Titles , EEE ECE EI Mech Dept Department Idea Report download


Engineering College Final Year project , Electrical and Electronics Department,Electronics and communication Department, Embedded Department , Mechanical Department (EEE Dept , ECE Dept., E&I Dept )

  1. A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories
  2. A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering
  3. A Computationally Efficient Delay less Frequency-Domain Adaptive Filter Algorithm
  4. A Linear Programming Based Tone Injection Algorithm for PAPR Reduction of OFDM and Linearly Precoded Systems
  5. A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks
  6. A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits
  7. Aliasing-Free Digital Pulse-Width Modulation for Burst-Mode RF Transmitters
  8. Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
  9. Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits
  10. Glitch-Free NAND-Based Digitally Controlled Delay-Lines
  11. IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures
  12. Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter with Low Adaptation-Delay
  13. Broadside and Skewed-Load Tests under Primary Input Constraints
  14. Built-In Generation of Functional Broadside Tests using a Fixed Hardware Structure
  15. Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip
  16. Design of Hardware Function Evaluators using Low-Overhead Nonuniform Segmentation with Address Remapping
  17. Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops
  18. Efficiency Optimization for Burst-Mode Multilevel Radio Frequency Transmitters
  19. Efficient Implementation of Reconfigurable Warped Digital Filters With Variable Low-Pass, High-Pass, Band pass, and Band stop Responses
  20. Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture
  21. Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function
  22. Eliminating Synchronization Latency Using Sequenced Latching
  23. Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes
  24. Low-Power Area-Efficient High-Speed I/O Circuit Techniques
  25. Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes
  26. Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic
  27. Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements
  28. MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems
  29. Multivoltage Aware Resistive Open Fault Model
  30. Oscillation and Transition Tests for Synchronous Sequential Circuits
  31. Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment
  32. RATS: Restoration-Aware Trace Signal Selection for Post-Silicon Validation
  33. Reduced-Complexity LCC Reed-Solomon Decoder Based on Unified Syndrome Computation
  34. Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories
  35. Smart Reliable Network-on-Chip
  36. Split-SAR ADCs: Improved Linearity With Power and Speed Optimization
  37. Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD
  38. Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches
  39. The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures
  40. Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed
  41. Time-Based All-Digital Technique for Analog Built-in Self-Test
  42. Two-Tone Phase Delay Control of Center Frequency and Bandwidth in Low-Noise-Amplifier RF Front Ends
  43. Unique Measurement and Modeling of Total Phase Noise in RF Receiver
  44. VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture
  45. WLS Design of Sparse FIR Digital Filters
  46. A 10-T SRAM cell with Inbuilt Charge Sharing for Dynamic Power Reduction 
  47. A Current-Starved Inverter-based Differential Amplifier Design for Ultra-Low Power Applications
  48. A Fast Low-Light Multi-Image Fusion with Online Image Restoration 
  49. A High Performance D-Flip Flop Design with Low Power Clocking System using MTCMOS
  50. A Low Power Fault Tolerant Reversible Decoder using MOS Transistor 
  51. A Low Power Single Phase Clock Distribution using VLSI technology 
  52. A Novel modulo Adder for 2n-2k-1 Residue Number System 
  53. A Novel Transistor Level Realization of Ultra Low Power High-Speed Adiabatic Vedic Multiplier 
  54. A Topology-Based Model for Railway Train Control Systems 
  55. Achieving Reduced Area by Multi-Bit Flip Flop Design
  56. An Analysis of SOBEL and GABOR Image Filters for Identifying Fish 
  57. An Efficient Denoising Architecture for Removal of Impulse Noise in Images 
  58. An Efficient High Speed Wallace Tree Multiplier 
  59. An Efficient SQRT Architecture of Carry Select Adder Design by Common Boolean Logic 
  60. An Interactive RFID-based Bracelet for Airport Luggage Tracking System 
  61. Area-Delay Efficient Binary Adders in QCA 
  62. Asynchronous Design of Energy Efficient Full Adder 
  63. Background Subtraction Based on Threshold detection using Modified K-Means Algorithm 
  64. Comparison of Static and Dynamic Printed Organic Shift Registers 
  65. CORDIC based Fast Radix-2 DCT Algorithm 
  66. Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA 
  67. Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating 
  68. Design of Digit-Serial FIR Filters: Algorithms, Architectures and a CAD Tool 
  69. Design of High Speed Low Power Viterbi Decoder for TCM System 
  70. Design of Low Energy, High Performance Synchronous and Asynchronous 64-Point FFT 
  71. Design of Low Power Sequential Circuit Using Clocked Pair Shared Flip flop 
  72. FFT Architectures for Real-Valued Signals Based on Radix-2by3 & Radix-2by4 Algorithms 
  73. Fixed-Width Multipliers and Multipliers- Accumulators with Min-Max Approximation Error
  74. FPGA Implementation of Pipelined Architecture For SPIHT Algorithm 
  75. Hardware Implementation of a Digital Watermarking System for Video Authentication 
  76. High-Throughput Compact Delay-Insensitive Asynchronous NOC Router 
  77. High-Throughput Multi standard Transform Core Supporting MPEG/H.264/VC-1 using Common Sharing Distributed Arithmetic 
  78. Improvement of the Security of Zigbee by a New Chaotic Algorithm 
  79. Least Significant Bit Matching Steganalysis based on Feature Analysis 
  80. Location-Aware and Safer Cards: Enhancing RFID Security and Privacy via Location Sensing 
  81. Low Latency Systolic Montgomery Multiplier for Finite Field Based on Pentanomials
  82. Low-Complexity Multiplier for GF (2m) based on All-One Polynomials
  83. Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Soft-core Processor
  84. Low-Power Digital Signal Processing Using Approximate Adders 
  85. Memory efficient high-Speed convolution-based generic structure for multilevel 2D DWT 
  86. Modified Gradient Search for Level Set Based Image Segmentation 
  87. Multicarrier Systems based on Multistage Layered IFFT Structure
  88. Optical Flow Estimation for Flame Detection in Videos 
  89. Parallel AES Encryption Engines for Many-Core Processor Arrays 
  90. Performance Analysis of a New CMOS Output Buffer 
  91. Performance Evaluation of FFT Processor Using Conventional and Vedic Algorithm 
  92. Pipelined Radix-2k Feed forward FFT Architectures 
  93. Prototype of a Fingerprint Based Licensing System For Driving 
  94. Real Time Communication between Multiple FPGA Systems in Multitasking Environment Using RTOS 
  95. Reconfigurable Processor for Binary Image Processing 
  96. Reduction of Leakage Current and Power in Full Subtractor Using MTCMOS Technique 
  97. Reverse Circle Cipher for Personal and Network Security 
  98. RFID-based Location System for Forest Search and Rescue Missions 
  99. RFID-based Tracking System Preventing Trees Extinction and Deforestation 
  100. Satellite Image Enhancement Using Discrete Wavelet Transform and Threshold Decomposition Driven Morphological Filter 
  101. Secure Transmission in Downlink Cellular Network with a Cooperative Jammer 
  102. Segmentation and Location of Abnormality in Brain MR Images using Distributed Estimation 
  103. Selective Eigen background for Background Modeling & Subtraction in Crowded Scenes 
  104. Shadow Removal for Background Subtraction Using Illumination Invariant Measures 
  105. Teaching HW/SW Co-Design with a Public Key Cryptography Application 
  106. Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes 
  107. The Security Technology and Tendency of New Energy Vehicle in Future
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Engineering College Final Year project Titles , EEE ECE EI Mech Dept Department Idea Report download : LIST OF IEEE VLSI PROJECTS 2018-2019 |

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