Digital System Design - EC25C07

 

EC25C07:

Digital System Design

 

Course Objective:

This course aims to create a strong foundation for Digital Electronics. The students are taught the basic components of digital systems and the processes of their implementation. The students are also taught Boolean algebra, logic gates, the basics of memories, and the implementation of combinational and sequential digital circuits using logic gates. Students are trained to employ the principles of digital electronics to implement digital design for the given problem.

 

Boolean Algebra:

Revisiting Boolean algebra and minimization, 4-variable Karnaugh Maps, SOP and POS Minimization using Karnaugh Maps-Introduction to Verilog HDL, Data Types and Operators-Different types of Modeling

 

Combinational Digital Circuits:

Introduction to combinational circuits, realization of logic expressions using AOI, NOR, and NAND gates. Adders, Subtractors, Multiplexers, De-multiplexers, Encoders, Decoders, Priority encoders, Arithmetic circuits, such as multipliers, Ripple adders, Code-converters –Programming using Verilog HDL.

Sequential Digital Circuits:

Introduction to sequential circuits, Moore and Mealy machine, Flip-flops and Latches, realization of flip-flops using S-R flip-flop, master slave flip-flop, JK flip-flop, T and D flip-flops, Realization of flip-flops using logic gates, introduction to shift registers, realization of different types of shift registers, introduction to counters, realization of different types of counters, Introduction to different types of memories Programming using Verilog HDL.

 

Finite State Machines:

Need for FSM, Elements of FSM, Components in FSM, FSM in HDL, Issues in FSM design, Case studies: Sequence detector, Odd parity Checker, Vending Machine

 

FPGA Architecture:

Introduction to FPGA Architecture, Components of FPGA Architectures – Programming Technologies, Logic elements and Look-up Tables, Dedicated multipliers, Distributed RAM, Shift registers, Digital Clock Managers, Altera FPGA and AMD Xilinx FPGA architectures and design flow-AMD Spartan, Virtex, Altera Cyclone, Arria and Agilex architectures-Introduction to IP Cores- AMD Microblaze V and Altera NIOS V Soft core processors

 

Weightage: Continuous Assessment: 40%, End Semester Examinations: 60%.

Assessment Methodology: Assignment (20%), Software activity (20%), Quiz (20%),

Internal Examinations (40%).

 

References:

1. Fletcher, W. I. (2015). An engineering approach to digital design (1st ed.). Pearson Education India.

2. Floyd, T. L. (2015). Digital fundamentals (11th ed., Global ed.). Pearson.

3. Mano, M. M., & Ciletti, M. D. (2019). Digital design: With an introduction to the Verilog HDL, VHDL, and SystemVerilog (6th ed., Global ed.). Pearson.

4. Roth, C. H., Jr., Kinney, L. L., & John, E. B. (2019). Fundamentals of logic design (7th ed.). Cengage.

5. Tocci, R. J., Widmer, N. S., & Moss, G. L. (2010). Digital systems: Principles and applications (11th ed.). Pearson Education.

6. Wakerly, J. F. (2018). Digital design: Principles and practices (5th ed.). Pearson Education.