Static Sequencing Element Methodology

STATIC SEQUENCING ELEMENT METHODOLOGY:

Power has become critical metric and key differentiator in sub-65nm SOC designs, due to growing power density driven by technology scaling and chip integration.

This tutorial provides overview of the low-power design methodologies and techniques in production SOC design perspective, emphasizing on the real design considerations and impact on chip success.

We shall discuss pros and cons of the methods and techniques considering impacts on chip.

This tutorial is organized in two parts. In the first part, we shall overview power related challenges in sub-60nm SOC design and state-of-the-art techniques to reduce chip power.

We shall give a holistic view from chip level to system and application levels. Practical industrial examples will be used to show how power savings can be achieved in modern SoC, processors and computer systems.

In the second part, we shall describe production low-power design methodology and techniques particularly the power-gating and the voltage/frequency scaling which are the two advanced power reduction methods used effectively in sub-65nm production low-power designs.

We shall explain when, where and how these methods and techniques are applied to a chip according to the design goals and time-to-market requirement.

We shall also cover production low-power design methodology and flow with UPF power intent and unified design environment.