Home | | Embedded Systems Design | Sharing bus bandwidth

Chapter: Embedded Systems Design : Basic peripherals

Sharing bus bandwidth

The DMA controller has to compete with the processor for external bus bandwidth to transfer data and as such can affect the processor’s performance directly.

Sharing bus bandwidth

 

The DMA controller has to compete with the processor for external bus bandwidth to transfer data and as such can affect the processor’s performance directly. With processors that do not have any cache or internal memory, such as the 80286 and the MC68000, their bus utilisation is about 80–95% of the bandwidth and therefore any delay in accessing external memory will result in a decreased processor performance budget and potentially longer interrupt latency — more about this in the chapter on interrupts.

For devices with caches and/or internal memory, their external bus bandwidth requirements are a lot lower and thus the DMA controller can use bus cycles without impeding the proces-sor’s performance. This last statement depends on the chances of the DMA controller using the bus at the same time as the proces-sor. This in turn depends on the frequency and size of the DMA transfers. To provide some form of flexibility for the designer so that a suitable trade-off can be made, most DMA controllers support different types of bus utilisation.

 

                                                                       Single transfer

 

Here the bus is returned back to the processor after every transfer so that the longest delay it will suffer in getting access to memory will be a bus cycle.

 

                                                                       Block transfer

 

Here the bus is returned back to the processor after the complete block has been sent so that the longest delay the processor will suffer will be the time of a bus cycle multi-plied by the number of transfers to move the block. In effect, the DMA controller has priority over the CPU in using the bus.

 

                                                                       Demand transfer

 

In this case, the DMA controller will hold the bus for as long as an external device requests it to do so. While the bus is held, the DMA controller is at liberty to transfer data as and when needed. In this respect, there may be gaps when the bus is retained but no data is transferred.

 



Study Material, Lecturing Notes, Assignment, Reference, Wiki description explanation, brief detail
Embedded Systems Design : Basic peripherals : Sharing bus bandwidth |


Privacy Policy, Terms and Conditions, DMCA Policy and Compliant

Copyright © 2018-2024 BrainKart.com; All Rights Reserved. Developed by Therithal info, Chennai.