Home | | VLSI Design | Power Dissipation - VLSI Design

Chapter: VLSI Design : Circuit Characterization and Simulation

Power Dissipation - VLSI Design

1. Software Level Power dissipation 2. Behavioral Level Power dissipation 3. Information Theoretic models

POWER DISSIPATION

 

The past the major concerns of the VLSI designer were area performance cost and reliability power considerations were mostly of only secondary importance.

 

In recent years how ever  this  has begun to change and increasingly power is being given comparable weight to area and speed.

 

Several factors have contributed to this trend Perhaps the primary driving factor has been the remarkable success and growth of the class of personal computing devices portable desktops audio and video based multimedia products and wireless communications systems.

 

Personal digital assistants and personal communicators which demand high speed computation and complex functionality with In the past the major concerns of the VLSI designer were area performance cost and reliability power considerations were mostly of only secondary importance.

 

In recent years however this has begun to change and increasingly power is being given comparable weight to area and speed.

 

Several factors have contributed to this trend Perhaps the primary driving factor has been the remarkable success and growth of the class of personal computing devices portable desktops audio and video based multimedia products and wireless communications systems personal digital assistants and personal communicators which demand high speed computation and complex functionality with low power consumption

 

There also exists a strong pressure for producers of high end products to reduce their power consumption.

 

1. Software Level Power dissipation

 

The first task in the estimation of power consumption of a digital system is to identify the typical application programs that will be executed on the system.

 

A non trivial application program consumes millions of machine cycles making it nearly impossible to perform power estimation using the complete program at say the RT level.

 

Most of the reported results are based on power macro modeling_ an estimation approach which is extensively used for behavioral and RTL level estimation.

 

In the power cost of a CPU module is characterized by estimating the average capacitance that would switch when the given CPU module is activated.

 

In the switching activities on address instruction a n d data b u s e s are used to estimate the Power consumption of  the  microprocessor, based on  actual current measurements of some processors Tiwarietal present the following instruction instruction level power model


Where

 

Energy p is the total energy dissipation of the program which is divided into three parts The first part is the summation of the base energy cost of each instruction, BCi is the base energy cost and Ni is the number of times instruction i is executed.

 

The second part accounts for the circuit state SCij is the energy cost when instruction i is followed by j during the program execution. Finally the third part accounts for energy contribution OCk of other instruction effects such as stalls and cache misses during the program execution.

 

In Hsieh et al present a new approach called profile driven program synthesis to perform RT level power estimation for high performance CPUs.

 

Instead of using a macro modeling equation to model the energy dissipation of a microprocessor the authors use a synthesized program to exercise the microprocessor in such a way that the resulting instruction trace behaves in terms of performance and power dissipation much the same as the original trace.

 

The new instruction trace is however much shorter than the original one and can hence be simulated on a RT level description of the target microprocessor to provide the power dissipation results quickly Specifically this approach consists of the following steps

 

§   Perform architectural simulation of the target microprocessor under the instruction trace of typical application programs

 

§   Extract characteristic p role including parameters such as the instruction mix Instruction data cache miss rates branch prediction miss rate pipeline stalls etc for the microprocessor.

 

§   Use mixed integer linear programming and heuristic rules to gradually transform a generic program template into a fully functional program.

 

§   Perform RT level simulation of the target microprocessor under the instruction trace of the new synthesized program.

 

Notice that the performance of the architectural simulator in gate vectors second is roughly to orders of magnitude higher than that of a RT level simulator.

 

This approach has been applied to the Intel Pentium processor which is a super scalar pipelined CPU with KB way set associative data instruction and data caches branch prediction and dual instruction pipeline demonstrating to orders of magnitude reduction in the RT level simulation time with negligible estimation error.

 

2. Behavioral Level Power dissipation

 

Conversely from some of the RT level methods that will be estimation techniques at the behavioral level cannot rely on information about the gate level structure of the design components and hence must resort to abstract notions of physical capacitance and switching activity to predict power dissipation in the design.

 

3. Information Theoretic models

 

Information theoretic approaches for high level power estimation depend on information theoretic measures of activity .for example entropy to obtain quick power estimates.

 

Entropy characterizes the randomness or uncertainty of a sequence of applied vectors and thus is intuitively related to switching activity that is if the signal switching is high it is likely that the bit sequence is random resulting in high entropy.

 

Suppose the sequence contains t distinct vectors and let pi denote the occurrence probability of any vector v in the sequence obviously

 

The entropy of the sequence is given


 

where log x denotes the base logarithm of x_ The entropy achieves its maximum value of log t when pi log pi For an n_bit vector(t,n)his makes the computation of the exact entropy very expensive. Assuming that the individual bits in the vector are independent_ then we can write


Where qi denotes the signal probability of bit i in the vector sequence. Note that this equation is only an upper bound on the exact entropy, since the bits may be dependent. This upper bound expression is however the one that is used for power estimation purposes.

 

The power dissipation in the circuit can be approximated as

 

Power=0.5V2CtotEavg

 

Where Ctot is the total capacitance of the logic module including gate and interconnect capacitances and Eavg is the average activity of each line in the circuit which is in turn approximated by one half of its average entropy havg.

 

The average line entropy is computed by abstracting information obtained from a gate level implementation. In it is assumed that the word level entropy per logic level reduces quadratic ally from circuit inputs to circuit outputs.

 

Whereas in it is assumed that the bit level entropy from one logic level to next decreases in an exponential manner. Based on these assumptions two different computational models are obtained

 

In M a r cu lescu et al derive a closed form expression for the average line entropy for the case of a linear gate distribution(i.e.,)when the number of nodes scales linearly between the number of circuit inputs n and circuit outputs m. The expression for havg is given by


 

where hin and hout denote the average bit level entropies of circuit inputs and outputs respectively hin is extracted from the given input sequence whereas hout is calculated from a quick functional simulation of the circuit under the given input sequence or by empirical entropy propagation techniques for pre characterized library modules.

In Nemani and Najm propose the following= expression for havg


 

where Hin and Hout denote the average sectional word level entropies of circuit inputs and outputs respectively.

 

The sectional entropy measures Hin and Hout may be obtained by monitoring the input and output signal values during a high level simulation of the circuit.

 

In practice however they are approximated as the summation of individual bit level entropies hin and hout. If the circuit structure is given the total module capacitance is calculated by traversing the circuit netlist and summing up the gate loadings.

 

Wire capacitances are estimated using statistical wire load models. Otherwise Ctot is estimated by quick mapping for example mapping to input universal gates or by information theoretic models that relate the gate complexity of a design to the divergence of its input and output entropies.

One such model proposed by Cheng and Agrawal  in for example estimates


 

This estimate tends to be too pessimistic when n is large hence in Ferrandi et al present a new total capacitance estimate based on the number N of nodes i.e.,to multiplexors in the Ordered Binary Decision Diagrams OBDD representation of the logic circuit as follows

 

The coefficients of the model are obtained empirically by doing linear regression analysis on the total capacitance values for a large number of synthesized circuits.

 

Entropic models for the controller circuitry are proposed by Tyagi in where three entropic lower bounds on the average Hamming distance bit changes with state set S and with T states are provided.


Study Material, Lecturing Notes, Assignment, Reference, Wiki description explanation, brief detail
VLSI Design : Circuit Characterization and Simulation : Power Dissipation - VLSI Design |


Privacy Policy, Terms and Conditions, DMCA Policy and Compliant

Copyright © 2018-2024 BrainKart.com; All Rights Reserved. Developed by Therithal info, Chennai.