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Drawing of the phasor diagram for a series RLC circuit energized by a sinusoidal voltage showing the relative position of current, component voltage and applied voltage for the following case
a) When XL > Xc
b) When XL < Xc
c) When XL = Xc.

**Drawing of the phasor diagram for a series RLC
circuit energized by a sinusoidal voltage showing the relative position of
current, component voltage and applied voltage for the following case**

**a)
****When X _{L} > Xc**

**b)
****When X _{L} < Xc**

**c)
****When X _{L} = Xc.**

__RLC Circuit:__

Consider a circuit in which R, L, and C are connected in series
with each other across ac supply as shown in fig.

The ac
supply is given by,

V = Vm sin wt

The
circuit draws a current I. Due to that different voltage drops are,

1) Voltage drop across Resistance R is V_{R}
= IR

2) Voltage drop across Inductance L is V_{L}
= IX_{L}

3) Voltage drop across Capacitance C is Vc = IXc The
characteristics of three drops are,

1. V_{R} is in phase with current I

2. V_{L} leads I by 90^{0}

3. Vc lags I by 90^{0}

According
to krichoff’s laws

__Steps to draw phasor diagram:__

1. Take current I as reference

2. V_{R} is in phase with current I

3. V_{L} leads current by 90^{0}

4. Vc lags current by 90^{0}

5. obtain resultant of V_{L} and Vc. Both
V_{L} and Vc are in phase opposition (180^{0} out of phase)

6. Add that with VRby law of parallelogram to
getsupply voltage.

The phasor diagram depends on the condition of magnitude of V_{L}
and Vc which ultimately depends on values of X_{L} and Xc.

Let us
consider different cases:

**Case(i): X**_{L}** > Xc**

When X _{L} > Xc

Also V_{L}
> Vc (or) IX_{L} > IXc

So, resultant of V_{L} and Vc will directed towards V_{L}
i.e. leading current I. Hence I lags V i.e. current I will lags the resultant
of V_{L} and Vc i.e. (V_{L} - Vc). The circuit is said to be
inductive in nature.

From
voltage triangle,

V = √ (V_{R}^{2} + (V_{L}
– Vc) ^{2}) = √ ((IR) ^{2} + (IX_{L} – IXc) ^{2})

V = I √ (R^{2} + (X_{L} – Xc) ^{2})

V = IZ

Z = √ (R^{2} + (X_{L} - Xc) ^{2}
)

If , V = Vm Sin wt ; i = Im Sin (wt - ф)

i.e I
lags V by angle ф

**Case(ii): X _{L} < Xc**

When X_{L}
< Xc

Also V_{L}
< Vc (or) IX_{L} < IXc

Hence the resultant of V_{L} and Vc will directed towards
Vc i.e current is said to be capacitive in nature Form voltage triangle

i.e I
lags V by angle ф

**Case(iii): X _{L} = Xc**

When X_{L}
= Xc

Also V_{L}
= Vc (or) IX_{L} = IXc

So V_{L} and Vc cancel each other and the resultant is
zero. So V = V_{R} in such a case, the circuit is purely resistive in
nature.

**Impedance:**

In general for RLC series circuit impedance is
given by,

Z = R + j X

X = X_{L} – Xc = Total reactance of the
circuit

If XL > Xc ; X
is positive & circuit is Inductive

If XL < Xc ; X
is negative & circuit is Capacitive

If XL = Xc ; X =0 & circuit is purely Resistive

Tan ф = [(X_{L} - Xc )∕R]

Cos ф = [R∕Z]

Z = √ (R^{2} + (X_{L} - Xc ) ^{2})

**Impedance
triangle:**

In both cases R = Z Cos ф

X = Z Sin ф

**Power
and power triangle:**

The average power consumed by circuit is,

Pavg = (Average power consumed by R) + (Average
power consumed by L) + (Average power consumed by C)

Pavg = Power taken by R = I^{2}R
= I(IR) = VI

V = V Cos ф

P = VI Cos ф

Thus, for any condition, X_{L} > Xc
or X_{L} < Xc General power can be expressed as

P = Voltage x Component in phase with voltage

**Power
triangle:**

S = Apparent power = I^{2}Z = VI

P = Real or True power = VI Cos ф = Active
power

Q = Reactive power = VI Sin ф

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