Parity Generator and Checker

Parity Generator and Checker:

Parity checkers are integrated circuits (ICs) used in digital systems to detect errors when streams of bits are sent from a transmitter to a receiver. Parity generators calculate the parity of data packets and add a parity amount to them. Both parity checkers and generators use parity memory, a basic form of error detection which provides an extra bit for every byte stored. Whenever a byte is written to memory, the parity circuit examines the byte and determines whether it contains an even or odd number of ones. If the data byte contains an even number of ones, the extra (parity) bit is set to 1; otherwise, the parity bit is set to 0. When the data is read back from memory, the parity circuit examines all of the bits and determines if there are an odd or even number of ones. An even number of ones indicates that there is an error in one of the bits because a parity circuit, when storing a byte, always sets an error-free parity bit to indicate an odd number of ones. When a parity error is detected, the parity circuit generates a non-maskable interrupt (NPI) that halts the processor, ensuring that the error does not corrupt other data.

There are several important performance specifications for parity checkers and generators. Number of bits is the number of words that devices can handle in parallel. Common configurations are 4, 5, 6, 8, 9, 12, or 16 bits. Supply voltages for parity checkers and generators range from - 5 V to 5 V and include intermediate voltages such as - 4.5 V, - 3.3 V, - 3 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V, and 3.6 V. Propagation delay is the time interval between the occurrence of a change at the output and the application of a change at the inputs. Operating temperature is a full-required range.

Selecting parity checkers and generators requires an analysis of logic families. Transistor-transistor logic (TTL) and related technologies such as Fairchild advanced Schottky TTL (FAST) use transistors as digital switches. By contrast, emitter coupled logic (ECL) uses transistors to steer current through gates that compute logical functions. Another logic family, complementary metal-oxide semiconductor (CMOS), uses a combination of p-type and n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. Bipolar CMOS (BiCMOS) is a silicon-germanium technology that combines the high speed of bipolar TTL with the low power consumption of CMOS. Other logic families for parity checkers and generators include cross-bar switch technology (CBT), gallium arsenide (GaAs), integrated injection logic (I²L) and silicon on sapphire (SOS). Gunning with transceiver logic (GTL) and gunning with transceiver logic plus (GTLP) are also available.

Parity checkers and generators are available in a variety of IC package types and with different numbers of pins. Basic IC package types for ALUs include ball grid array (BGA), quad flat package (QFP), single in-line package (SIP), and dual in-line package (DIP). Many packaging variants are available. For example, BGA variants include plastic-ball grid array (PBGA) and tape-ball grid array (TBGA). QFP variants include low-profile quad flat package (LQFP) and thin quad flat package (TQFP). DIPs are available in either ceramic (CDIP) or plastic (PDIP). Other IC package types include small outline package (SOP), thin small outline package (TSOP), and shrink small outline package (SSOP).

Transistor–transistor logic (TTL) is a class of digital circuits built from bipolar junction transistors (BJT) and resistors. It is called transistor–transistor logic because both the logic gating function (e.g., AND) and the amplifying function are performed by transistors (contrast this with RTL and DTL).

TTL is notable for being a widespread integrated circuit (IC) family used in many applications such as computers, industrial controls, test equipment and instrumentation, consumer electronics, synthesizers, etc. The designation TTL is sometimes used to mean TTL-compatible logic levels, even when not associated directly with TTL integrated circuits, for example as a label on the inputs and outputs of electronic instruments.

Fundamental TTL gate

TTL is a natural successor of DTL since it is based on the same fundamental concept - implementing the logic gate function by using the base-emitter junctions of a multiple-emitter transistor as switching elements like DTL input diodes. This IC structure is functionally equivalent to multiple transistors where the bases and collectors are tied together. The output of the simple TTL gate is buffered, like DTL, by a common emitter amplifier.

Input logical ones. When all the inputs are held at high voltage the base-emitter junctions of the multiple-emitter transistor are backward-biased. In contrast with

DTL, small (about 10 μA) "collector" currents are drawn by the inputs since the transistor is in a reverse-active mode (with swapped collector and emitter). The base resistor in combination with the supply voltage acts as a substantially constant current source. It passes current through the base–collector junction of the multiple-emitter transistor and the base-emitter junction of the output transistor thus turning it on; the output voltage becomes low (logical zero).

Input logical zero. If one input voltage becomes zero, the corresponding base-emitter junction of the multiple-emitter transistor connects in parallel to the two connected in series junctions (the base-collector junction of the multiple-emitter transistor and the base-emitter junction of the second transistor). The input base-emitter junction steers all the base current of the output transistor to the input source (the ground). The base of the output transistor is deprived of current causing it to go into cut-off and the output voltage becomes high (logical one). During the transition the input transistor is briefly in its active region; so it draws a large current away from the base of the output transistor and thus quickly discharges its base. This is a critical advantage of TTL over DTL that speeds up the transition over a diode input structure.

The main disadvantage of TTL with a simple output stage is the relatively high output resistance at output logical "1" that is completely determined by the output collector resistor. It limits the number of inputs that can be connected (the fan out). Some advantage of the simple output stage is the high voltage level (up to V_CC) of the output logical "1" when the output is not loaded.

Logic of this type is most frequently encountered with the collector resistor of the output transistor omitted, making an open collector output. This allows the designer to fabricate logic by connecting the open collector outputs of several logic gates together and providing a single external pull-up resistor. If any of the logic gates becomes logic low (transistor conducting), the combined output will be low. Examples of this type of gate are the 7401and 7403 series.

TTL with a "totem-pole" output stage

To solve the problem with the high output resistance of the simple output stage the second schematic adds to this a "totem-pole" ("push-pull") output. It consists of the two n-p-n transistors V₃ and V₄, the "lifting" diode V₅ and the current-limiting resistor R₃ (see the figure on the right). It is driven by applying the same current steering idea.

When V₂ is "off", V₄ is "off" as well and V₃ operates in active region as a voltage follower producing high output voltage (logical "1"). When V₂ is "on", it activates V₄, driving low voltage (logical "0") to the output. V₂ and V₄ collector–emitter junctions connect V₄ base-emitter junction in parallel to the series-connected V₃ base-emitter and V₅ anode-cathode junctions. V₃ base current is deprived; the transistor turns "off" and it does not impact on the output. In the middle of the transition, the resistor R₃ limits the current flowing directly through the series connected transistor V₃, diode V₅ and transistor V₄ that all are conducting. It also limits the output current in the case of output logical "1" and short connection to the ground. The strength of the gate may be increased without proportionally affecting the power consumption by removing the pull-up and pull-down resistors from the output stage.

The main advantage of TTL with a "totem-pole" output stage is the low output resistance at output logical "1". It is determined by the upper output transistor V₃ operating in active region as a voltage follower. The resistor R₃ does not increase the output resistance since it is connected in the V₃ collector and its influence is compensated by the negative feedback. A disadvantage of the "totem-pole" output stage is the decreased voltage level (no more than 3.5 V) of the output logical "1" (even, if the output is unloaded). The reason of this reduction are the voltage drops across the V₃ base-emitter and V₅ anode-cathode junctions.