Home | | VLSI Design | Manufacturing Test

Chapter: VLSI Design : CMOS Testing

Manufacturing Test

A speck of dust on a wafer is sufficient to kill chip Yield of any chip is < 100% Must test chips after manufacturing before delivery to customers to only ship good parts Manufacturing testers are very expensive Minimize time on tester Careful selection of test vectors.

MANUFACTURING TEST

 

A speck of dust on a wafer is sufficient to kill chip Yield of any chip is < 100% Must test chips after manufacturing before delivery to customers to only ship good parts Manufacturing testers are very expensive Minimize time on tester Careful selection of test vectors.

 

A test for a defect will produce an output response which is different from the output when there is no defect Test quality is high if the set of tests will detect a very high fraction of possible defects Defect level is the percentage of bad parts shipped to customers Yield is the percentage of defect-free chips manufactured

 

1. Fault models:

 

Numerous possible physical failures (what we are testing for) Can reduce the number of failure types by considering the effects of physical failures on the logic functional blocks: called a Assume that defects will cause the circuit to behave as if lines were “stuck” at logic 0 or 1 Most commercial tools for test are based on the “stuck-at” model Other fault models “Stuck open” model for charge retained on a CMOS node Recent use of the “transition” fault model in an attempt to deal with delays “Path delay” fault model would be better for small delay defects, but the large number of possible paths is an impediment to the use of this fault model.

Study Material, Lecturing Notes, Assignment, Reference, Wiki description explanation, brief detail
VLSI Design : CMOS Testing : Manufacturing Test |


Privacy Policy, Terms and Conditions, DMCA Policy and Compliant

Copyright © 2018-2024 BrainKart.com; All Rights Reserved. Developed by Therithal info, Chennai.