Differential amplifier

Differential amplifier

The function of a differential amplifier is to amplify the difference between two signals. The need for differential amplifier arises in many physical measurements where response from DC to many MHz of frequency is required. This forms the basic input stage of an integrated amplifier.

The basic differential amplifier has the following important properties of

·           Excellent stability

·           High versatility and

·           High immunity to interference signals

The differential amplifier as a building block of the op-amp has the advantages of

·           Lower cost

·           Easier fabrication as IC component and

·           closely matched components.

The above figure shows the basic block diagram of a differential amplifier, with two input terminals and one output terminal. The output signal of the differential amplifier is proportional to the difference between the two input signals.

V₀ = A_dm ( V₁ – V₂ )

If  V₁ = V₂, then the output voltage is zero. A non-zero output voltage V0 is obtained when  V₁ and V₂ are not equal. The difference mode input voltage is defined as V_m =  V₁ – V₂ and the common mode input voltage is defined as

These equation show that if  V₁ = V₂, then the differential mode input signal is zero and common mode input signal is V_cm =  V₁ =V₂.

Differential Amplifier with Active load:

Differential amplifier is designed with active loads to increase the differential mode voltage gain. The open circuit voltage gain of an op-amp is needed to be as large as possible. This is got by cascading the gain stages which increase the phase shift and the amplifier also becomes vulnerable to oscillations. The gain can be increased by using large values of collector resistance. For such a circuit, the voltage gain is given by

A_dm = gm RC

To increase the gain the IC RC product must be made very large. However, there are limitations in IC fabrication such as,

1.        A large value of resistance needs a large chip area.

2.        For large RC, the quiescent drop across the resistor increase and a large power supply will be required to maintain a given operating current.

3.        Large monolithic resistor introduces large parasitic capacitances which limits the frequency response of the amplifier.

4.        for linear operation of the differential pair, the devices should not be allowed to enter into saturation. This limits the max input voltage that can be applied to the bases of transistors Q₁ and Q₂ the base-collector junction must be allowed to become forward-biased by more than 0.5V. The large value of load resistance produces a large dc voltage drop (I_EE / 2) R_C, so that the collector voltage will be V_C=Vcc - (IEE/2) RC and it will be substantially less than the supply voltage Vcc. This will reduce the input voltage range of the differential amplifier. Due to the reasons cited above, an active load is preferred in the differential amplifier configurations.

BJT Differential Amplifier using active loads:

A simple active load circuit for a differential amplifier is the current mirror active load as shown in figure. The active load comprises of transistors Q₃ and Q₄ with the transistor Q₃ connected as a Diode with its base and collector shorted. The circuit is shown to drive a load RL. When an ac input voltage is applied to the differential amplifier, the various currents of the circuit are given by I_C4 = I_C3 = I_C1 = gmVid/2 where I_C4 = I_C3 due to current mirror action.

I_C2 = - gmVid/2 .

We know that the load current IL entering the next stage is I_L= I_C2-I_C4 = - gmVid/2 - gmVid/2 = - gmVid

Then, the output voltage from the differential= amplifier= is given by V₀= - I_LR_L = gm R_LV_id. The ac voltage gain of the circuit is given by A_v = v₀/v_id = gmR_L. The amplifier can amplify the differential input signals and it provides single-ended output with a ground reference since the load R_L is connected to only one output terminal. This is made possible by the use of the current mirror active load. The output resistance R0 of the circuit is that offered by the parallel combination of transistors Q₂ (NPN) and Q₄ (PNP). It is given by R_r = r₀₂ || r₀₄.

Analysis of BJT differential amplifier with active load:

The collector currents of all the transistors are equal.

I_C1 = I_C2 = I_C3 =I_C4 = I_EE/2 .

The Collector -emitter voltages of Q₁ and Q₂ are given by

V_CE1-V_CE2 =V_C-V_E=V_CC - V_EB-(-V_EB)= V_CC

Eqn. shows that, the offset is higher than that of a resistive loaded differential amplifier A. This can be reduced by the use of emitter resistors for Q₃ and Q₄ , and a transistor Q₅ in the current mirror load.

CMRR of the differential amplifier using active load:

The differential amplifier using active load provides high voltage gain to the differential input signal and a single – ended output that is referenced to the ground is obtained. The differential amplifier which provides conversion for a differential signal to a single ended signal is necessary in differential input signal ended output amplifiers. The op-amp is one such circuit. The changes in the common-mode signal of the bias current source. This induces a change in I_C2 and an identical change in I_C1. The change in I_C1 will then produce a change in the PNP load devices, and thereby a change in I_C4, which is the collector current Q₄, The current I_C4 is in such a direction as to cancel the change in I_C2. As a result of this, any common mode input does not cause a change in output.

The voltage gain of the differential amplifier is independent of the quiescent current I_EE. This makes it possible to use very small value of I_EE as low as 20μA, while still maintaining a large voltage gain. Small value of I_EE is preferred, since it results in a small value of bias current and a large value for the input resistance. A limitation in choosing a small I_EE is, however, the fact that, it will result in a poor frequency response of the amplifier.

When a small value of bias current is required, the best approach is to use a JFET or MOSFET differential amplifier that is operated at comparatively higher values of I_EE.

Differential Mode signal analysis:

The ac analysis of the differential amplifier can be made using the circuit model as shown below. The differential input transistor pair produces equal and opposite currents whose amplitude us given by gm2 V_id /2 at the collector of Q₁ and Q₂. The collector current I_c1 is fed by the transistor Q₃ and it is mirrored at the output of Q₄. Therefore, the total current i₀ flowing through the load resistor R_L is given by i₀ = [2g_m2V_id]/2 = g_m2V_id.

Then the output voltage is  v₀ =i₀R_L – g_m2R_Lv_id and the differential mode gain Ad of the differential amplifier is

This current mirror provides a single ended output which has a voltage equal to the maximum gain of the common emitter amplifier.

The power of the current mirror can be increased by including additional common collector stages at the o/p of the differential input stage. A bipolar differential amplifier structure with additional stages is shown in figure. The resistance at the output of the differential stage is now given by the parallel combination of transistors Q₂ and Q₄ and the input resistance is offered by Q₅. Then, the equivalent resistance is expressed by Req = r_o2 || r₀₄ || r_i5 = r_i5.

The gain of the differential stage then becomes  Adm  = g_m2 R_eq = g_m2 r_i5=βI_C2/I_C5 .